Staff Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The focus of this role is to plan, build, and execute the design of new and existing features for AMD’s IP (involving System reset and boot, clocking, advanced power management as well as some sub-IP controllers), resulting in no bugs in the final design. It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM architecture, AMBA(AXI/AHB/APB) bus, USB(4.0/3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/eSPI/GPIO), General connectivity IPs (I2C/I3C/UART), Ethernet, JTAG, SoC IP integration, etc. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Understand the ASIC design/verification flow to deliver high quality IP to SoCs and meet power, area, timing, schedule bounding box, and other metrics The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: specification, microarchitecture definition, top level SOC design tasks, HDL coding, simulation debugging, timing, silicon debugging, etc. PREFERRED EXPERIENCE: Master in Electrical Engineering, Computer Science or related Good understanding on ASIC design verification flow Strong RTL coding skills with Verilog/System Verilog Familiar with Front-End design and implementation flow Knowledge on synthesis, STA, CDC, RDC, UPF, etc. Strong knowledge on AMBA(AXI/AHB/APB) bus Good experience on system IP design in complex SoC, system reset and boot, advanced power management, clocking and etc Low power design experience, or Network-on-chip experience is a plus Scripting language experience: Perl, Ruby, Makefile, shell preferred Strong analytical and problem-solving skills Excellent communication skills and experience collaborating with global projects colleague Fluent English communication skills(listening, speaking and writing)    Exposure to leadership or mentorship is an asset. ACADEMIC CREDENTIALS: Bachelors or above degree in computer engineering/Electrical Engineering. LOCATION: Penang, Malaysia #LI-KL1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

THE ROLE: The focus of this role is to plan, build, and execute the design of new and existing features for AMD’s IP (involving System reset and boot, clocking, advanced power management as well as some sub-IP controllers), resulting in no bugs in the final design. It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM architecture, AMBA(AXI/AHB/APB) bus, USB(4.0/3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/eSPI/GPIO), General connectivity IPs (I2C/I3C/UART), Ethernet, JTAG, SoC IP integration, etc. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Understand the ASIC design/verification flow to deliver high quality IP to SoCs and meet power, area, timing, schedule bounding box, and other metrics The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: specification, microarchitecture definition, top level SOC design tasks, HDL coding, simulation debugging, timing, silicon debugging, etc. PREFERRED EXPERIENCE: Master in Electrical Engineering, Computer Science or related Good understanding on ASIC design verification flow Strong RTL coding skills with Verilog/System Verilog Familiar with Front-End design and implementation flow Knowledge on synthesis, STA, CDC, RDC, UPF, etc. Strong knowledge on AMBA(AXI/AHB/APB) bus Good experience on system IP design in complex SoC, system reset and boot, advanced power management, clocking and etc Low power design experience, or Network-on-chip experience is a plus Scripting language experience: Perl, Ruby, Makefile, shell preferred Strong analytical and problem-solving skills Excellent communication skills and experience collaborating with global projects colleague Fluent English communication skills(listening, speaking and writing)    Exposure to leadership or mentorship is an asset. ACADEMIC CREDENTIALS: Bachelors or above degree in computer engineering/Electrical Engineering. LOCATION: Penang, Malaysia #LI-KL1 #LI-Hybrid

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Tags: No, MYR RM119,700.00/Yr., MYR RM171,000.00/Yr., Global Careers (do not use for US or Canada)