Sr. Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the Strategic Silicon Solution Group Full Chip Low Power Design and Signoff team, you will help bring to life cutting-edge designs. You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. THE PERSON: A successful candidate should have 9+ years of minimum experience. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power design/signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Expertise in Full Chip Power Delivery Network Design, Implementation and Signoff Must have good understanding of RDL & Power grid design. Must know the NPV Static, Dynamic & SEM Run. Must have good experience of Vectored dynamic, CPM & Ramp up time analysis and current analysis. Must have experience on Full chip, Sub-system level & tile/block/partition level EMIR analysis and signoff Should have good knowledge of package level EMIR analysis. Expertise in low power design and implementation such as clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption. Should have good knowledge on simulation of special cell’s with target power analysis. Should possess good knowledge of Power switch insertion, Secondary PG design towards improvising PPA. Mentor/coach/guide design engineers to achieve the project goal. Should have hands on experience on tools like Redhawk-SC, ICC2 & Prime Time or equivalent industry standard tools. Should have good scripting experience in Shell, Python, Perl, TCL, UNIX PREFERRED EXPERIENCE: Understanding of ICC2 or Fusion Compiler Physical Design flows/methodologies or equivalent tools. Expertise on tool expected. Experience in TCL/Python and other languages needed. Should be strong in scripting and decode/debug old existing scripts. Experience with RHSC, PTPX, ICC2, Fusion Compiler Experience with mentoring a team on lower tech node (5/3nm) projects on PDN (EMIR) Experience in Full Chip/Sub-system level Physical Verification including DRC, LVS, DFM, ESD, High voltage checks etc, ACADEMIC CREDENTIALS: Bachelors or Master's degree in Computer/Electronics/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SENIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the Strategic Silicon Solution Group Full Chip Low Power Design and Signoff team, you will help bring to life cutting-edge designs. You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. THE PERSON: A successful candidate should have 9+ years of minimum experience. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power design/signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Expertise in Full Chip Power Delivery Network Design, Implementation and Signoff Must have good understanding of RDL & Power grid design. Must know the NPV Static, Dynamic & SEM Run. Must have good experience of Vectored dynamic, CPM & Ramp up time analysis and current analysis. Must have experience on Full chip, Sub-system level & tile/block/partition level EMIR analysis and signoff Should have good knowledge of package level EMIR analysis. Expertise in low power design and implementation such as clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption. Should have good knowledge on simulation of special cell’s with target power analysis. Should possess good knowledge of Power switch insertion, Secondary PG design towards improvising PPA. Mentor/coach/guide design engineers to achieve the project goal. Should have hands on experience on tools like Redhawk-SC, ICC2 & Prime Time or equivalent industry standard tools. Should have good scripting experience in Shell, Python, Perl, TCL, UNIX PREFERRED EXPERIENCE: Understanding of ICC2 or Fusion Compiler Physical Design flows/methodologies or equivalent tools. Expertise on tool expected. Experience in TCL/Python and other languages needed. Should be strong in scripting and decode/debug old existing scripts. Experience with RHSC, PTPX, ICC2, Fusion Compiler Experience with mentoring a team on lower tech node (5/3nm) projects on PDN (EMIR) Experience in Full Chip/Sub-system level Physical Verification including DRC, LVS, DFM, ESD, High voltage checks etc, ACADEMIC CREDENTIALS: Bachelors or Master's degree in Computer/Electronics/Electrical Engineering #LI-SR4

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Tags: No, INR ₹1,848,000.00/Yr., INR ₹2,640,000.00/Yr., Global Careers (do not use for US or Canada)