Senior Physical Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This is an exciting opportunity to join the innovative and multi-award winning team that has developed the RF data converter sub-system, including direct-RF digital signal processing, around which Zynq® Ultrascale+™ RFSoC is built. As part of the Analog and Digital-RF design group you will help to develop a wide range of ultra challenging, high instance count (1-5M), high speed (>1G), high utilization, low power digital IPs as part of a highly collaborative mixed-signal team using the latest FinFET CMOS processes. We are hiring across Senior to Principal levels, with opportunities available in Cork, Dublin, and Edinburgh. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Synthesis flow development and delivery STA development and signoff Physical implementation waiver development and signoff Interfacing to front end, place & route, DFx, verification, CAD, and silicon validation teams to discuss and resolve timing, power, coverage, silicon, and other issues Timing constraint development and maintenance Interacting with analog team to define analog/digital interfaces and specification PREFERRED EXPERIENCE: A proactive, and highly collaborative approach to problem solving Knowledge of physical, synthesis and static timing considerations such as timing constraints and implementation for low power, high speed and minimum area Experience collaborating with front end, place & route, DFx, verification, CAD and silicon validation teams Understanding of RTL to GDSII flows, including BEQ, Constraints Validation, DFx insertion, Timing ECO, Power Analysis, and EMIR Understanding of timing library characterizations, static timing margining and SPICE simulations Intertest in evaluating, developing and adopting AI, complex UPF and other next generation initiatives in design flows and methodologies A strong record of continuous improvement, including the use of TCL, Perl/Python and shell scripting A strong record of collaboration and knowledge sharing Experience using ultra advanced technology nodes Experience with Vivado, Virtuoso, SPICE, Liberate AMS, and gate level simulations Experience of working in mixed-signal designs and interfacing between analog and digital domains A proactive, and highly collaborative approach to problem solving Knowledge of physical, synthesis and static timing considerations such as timing constraints and implementation for low power, high speed and minimum area Experience using AI, ChatGPT, Claude etc. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PL1 #LI-Hybrid #Cork #Dublin #Edinburgh Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

THE ROLE: This is an exciting opportunity to join the innovative and multi-award winning team that has developed the RF data converter sub-system, including direct-RF digital signal processing, around which Zynq® Ultrascale+™ RFSoC is built. As part of the Analog and Digital-RF design group you will help to develop a wide range of ultra challenging, high instance count (1-5M), high speed (>1G), high utilization, low power digital IPs as part of a highly collaborative mixed-signal team using the latest FinFET CMOS processes. We are hiring across Senior to Principal levels, with opportunities available in Cork, Dublin, and Edinburgh. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Synthesis flow development and delivery STA development and signoff Physical implementation waiver development and signoff Interfacing to front end, place & route, DFx, verification, CAD, and silicon validation teams to discuss and resolve timing, power, coverage, silicon, and other issues Timing constraint development and maintenance Interacting with analog team to define analog/digital interfaces and specification PREFERRED EXPERIENCE: A proactive, and highly collaborative approach to problem solving Knowledge of physical, synthesis and static timing considerations such as timing constraints and implementation for low power, high speed and minimum area Experience collaborating with front end, place & route, DFx, verification, CAD and silicon validation teams Understanding of RTL to GDSII flows, including BEQ, Constraints Validation, DFx insertion, Timing ECO, Power Analysis, and EMIR Understanding of timing library characterizations, static timing margining and SPICE simulations Intertest in evaluating, developing and adopting AI, complex UPF and other next generation initiatives in design flows and methodologies A strong record of continuous improvement, including the use of TCL, Perl/Python and shell scripting A strong record of collaboration and knowledge sharing Experience using ultra advanced technology nodes Experience with Vivado, Virtuoso, SPICE, Liberate AMS, and gate level simulations Experience of working in mixed-signal designs and interfacing between analog and digital domains A proactive, and highly collaborative approach to problem solving Knowledge of physical, synthesis and static timing considerations such as timing constraints and implementation for low power, high speed and minimum area Experience using AI, ChatGPT, Claude etc. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PL1 #LI-Hybrid #Cork #Dublin #Edinburgh

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Tags: No, EUR €44,800.00/Yr., EUR €64,000.00/Yr., Global Careers (do not use for US or Canada)