Sr. Manager Silicon Design Engineering (DDR verification)

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: AMD is looking for an experienced Design Verification Manager/Lead willing to take on the challenges of leading a Design Verification team within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as highly configurable high-speed memory I/Os/PHYs and Chiplet Interconnect IP (e.g. UCIE) to various Business Units/SoCs within AMD. The DV team is responsible for functional verification of these IP by creating advanced testbenches and using leading-edge verification techniques. A successful candidate will work with architects and fellow design and verification leads. The candidate will be detail-oriented, possessing strong communication, mentoring, leadership and problem-solving skills. Can work well with cross functional teams. Skilled at driving team and tasks from start to completion with superior quality. Drives to learn and perform at his or her highest potential in a technical capacity. Flexible in working hours to accommodate working with co-workers in different time-zones. KEY RESPONSIBILITIES: Manage and lead a team of design verification engineers with focus on mixed-signal IP (MSIP) verification domain. Own the plan and lead the verif team activities on functional verification execution from test plan to verification signoff. Planning includes resource estimation and allocation to ensure high confidence execution. Responsibilities high level planning, work breakdown planning, tasks assignments and progress tracking, schedule and priority management, performance review, mentor, talent development, and hiring. Work with project/program managers, SOC/sub-system architects, AMS designers and physical designers to guarantee quality/timely deliverables meeting schedule and technical requirements and providing strong support to customers Collaborate with MSIP architects and designers to understand the IP and/or Sub-System features. Write/Implement/Review Test Plans for all layers of the design including digital, mixed signal and analog parts. Verification of critical high speed digital designs using coverage driven random and directed testing techniques as well as Formal Verification. Own all aspects of the Verification flow from initial test planning to coverage convergence and sign-off for one or more IP. Build testbench components as well as test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology. Conduct and participate in Test Reviews for each plan milestone, including tapeout readiness reviews. Technical leadership, including driving IP projects from start to the finish and Design verification sign-off. PREFERRED EXPERIENCE: Proven experience in verifying commercially successful IPs, Sub-Systems or SoCs. Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, must have strong technical management skills and provide a positive influence on team morale and culture. Experience with work and task breakdown and planning, and IP project management. Must be expert in SystemVerilog, UVM. Proficient in object-oriented programming, scripting (Shell/Python/Perl/Tcl/Ruby), and low-level programming languages. Deep system architecture knowledge of Memory Systems(DDR/LPDDR/HBM),high speed I/O interconnects technologies (UCIE, …) and PHYs desirable. Excellent knowledge of standard bus interface protocols (i.e., RDI, PIPE, DFI etc). Experience in Verification of Multi-Voltage Domain designs Analog/Digital co-verification experience a plus including Industry verification experience with Mixed-Signal blocks and SOCs. Expertise building/using Mixed-Signal testbenches, checkers and tests using System Verilog and in creating and/or using real-numbered analog behavioral models in System Verilog/Verilog-AMS are highly desirable. Self-motivated, disciplined, organized, and detailed orientated. Able to drive independently to solve problems and to be collaborative with the global org/global AMD design community to identify optimum solutions to novel problems. Strike the right balance between the speed and quality of required decisions. Strong communications, time management and presentation skills combined with broad technical skills. This is a highly visible role in which the team will look to you as the guide for leading execution and design activities on a day-to-day basis. ACADEMIC CREDENTIALS: PhD/MS/BS in Electrical Engineering or Computer Engineering or related equivalent #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: AMD is looking for an experienced Design Verification Manager/Lead willing to take on the challenges of leading a Design Verification team within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as highly configurable high-speed memory I/Os/PHYs and Chiplet Interconnect IP (e.g. UCIE) to various Business Units/SoCs within AMD. The DV team is responsible for functional verification of these IP by creating advanced testbenches and using leading-edge verification techniques. A successful candidate will work with architects and fellow design and verification leads. The candidate will be detail-oriented, possessing strong communication, mentoring, leadership and problem-solving skills. Can work well with cross functional teams. Skilled at driving team and tasks from start to completion with superior quality. Drives to learn and perform at his or her highest potential in a technical capacity. Flexible in working hours to accommodate working with co-workers in different time-zones. KEY RESPONSIBILITIES: Manage and lead a team of design verification engineers with focus on mixed-signal IP (MSIP) verification domain. Own the plan and lead the verif team activities on functional verification execution from test plan to verification signoff. Planning includes resource estimation and allocation to ensure high confidence execution. Responsibilities high level planning, work breakdown planning, tasks assignments and progress tracking, schedule and priority management, performance review, mentor, talent development, and hiring. Work with project/program managers, SOC/sub-system architects, AMS designers and physical designers to guarantee quality/timely deliverables meeting schedule and technical requirements and providing strong support to customers Collaborate with MSIP architects and designers to understand the IP and/or Sub-System features. Write/Implement/Review Test Plans for all layers of the design including digital, mixed signal and analog parts. Verification of critical high speed digital designs using coverage driven random and directed testing techniques as well as Formal Verification. Own all aspects of the Verification flow from initial test planning to coverage convergence and sign-off for one or more IP. Build testbench components as well as test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology. Conduct and participate in Test Reviews for each plan milestone, including tapeout readiness reviews. Technical leadership, including driving IP projects from start to the finish and Design verification sign-off. PREFERRED EXPERIENCE: Proven experience in verifying commercially successful IPs, Sub-Systems or SoCs. Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, must have strong technical management skills and provide a positive influence on team morale and culture. Experience with work and task breakdown and planning, and IP project management. Must be expert in SystemVerilog, UVM. Proficient in object-oriented programming, scripting (Shell/Python/Perl/Tcl/Ruby), and low-level programming languages. Deep system architecture knowledge of Memory Systems(DDR/LPDDR/HBM),high speed I/O interconnects technologies (UCIE, …) and PHYs desirable. Excellent knowledge of standard bus interface protocols (i.e., RDI, PIPE, DFI etc). Experience in Verification of Multi-Voltage Domain designs Analog/Digital co-verification experience a plus including Industry verification experience with Mixed-Signal blocks and SOCs. Expertise building/using Mixed-Signal testbenches, checkers and tests using System Verilog and in creating and/or using real-numbered analog behavioral models in System Verilog/Verilog-AMS are highly desirable. Self-motivated, disciplined, organized, and detailed orientated. Able to drive independently to solve problems and to be collaborative with the global org/global AMD design community to identify optimum solutions to novel problems. Strike the right balance between the speed and quality of required decisions. Strong communications, time management and presentation skills combined with broad technical skills. This is a highly visible role in which the team will look to you as the guide for leading execution and design activities on a day-to-day basis. ACADEMIC CREDENTIALS: PhD/MS/BS in Electrical Engineering or Computer Engineering or related equivalent #LI-PK2

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Tags: No, INR ₹5,426,470.00/Yr., INR ₹7,752,100.00/Yr., Global Careers (do not use for US or Canada)