Senior DFT Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.  

 

MTS SILICON DESIGN ENGINEER  

  

 

THE ROLE: 

The focus of this role is to plan, build, and execute the DFT verification of new and existing features for AMD’s Chiplets , resulting in no bugs in the final design.

 

THE PERSON:

As a DFx Verification Engineer, you will be primarily responsible for verification of architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products and will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference.

 

KEY RESPONSIBILITIES:

• Collaborate with architects, design engineers, and firmware engineers to understand the new DFT features to be verified 
• Estimate the time required to write the new feature tests and any required changes to the test environment 
• Build the directed and random DFT verification tests 
• Debug test failures to determine the root cause; work with RTL/DFT and firmware engineers to resolve design defects and correct any test issues
• Analyze and enhance legacy DFT test plans to accommodate new Design for Debug feature developments
• Write complex Perl scripts to update simulation files in a deterministic manner
• Recreate post-silicon failures in pre-silicon environment
• Conduct silicon debug and root cause analysis with minimal logging support
• Utilize JTAG protocols for debugging and validation

 

PREFERRED EXPERIENCE:

• 8+ years of experience in DFT Design Verification with strong debug capabilities
• Experienced with SystemVerilog/UVM testbench development for complex SoCs Including GLS & SDF verifications
• Advanced scripting skills (Python, Perl, etc.) for automation and testbench infrastructure
• Deep knowledge of digital design, RTL design, and verification flows
• Strong troubleshooting and analytical debugging skills with ability to debug without logs
•  Ability to quickly adapt to complex infrastructure environments
•  Excellent hands-on debug skills and attention to detail
• Proficient in debugging firmware and RTL code using simulation tools
• Exposure to leadership or mentorship is an asset 

 

 

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

#LI-PM2

Benefits offered are described: AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

 

MTS SILICON DESIGN ENGINEER  

  

 

THE ROLE: 

The focus of this role is to plan, build, and execute the DFT verification of new and existing features for AMD’s Chiplets , resulting in no bugs in the final design.  

 

  

THE PERSON:  

As a DFx Verification Engineer, you will be primarily responsible for verification of architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products and will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference.

 

  

KEY RESPONSIBILITIES:  

• Collaborate with architects, design engineers, and firmware engineers to understand the new DFT features to be verified 
• Estimate the time required to write the new feature tests and any required changes to the test environment 
• Build the directed and random DFT verification tests 
• Debug test failures to determine the root cause; work with RTL/DFT and firmware engineers to resolve design defects and correct any test issues  
• Analyze and enhance legacy DFT test plans to accommodate new Design for Debug feature developments
• Write complex Perl scripts to update simulation files in a deterministic manner
• Recreate post-silicon failures in pre-silicon environment
• Conduct silicon debug and root cause analysis with minimal logging support
• Utilize JTAG protocols for debugging and validation

  

 

PREFERRED EXPERIENCE:  

• 8+ years of experience in DFT Design Verification with strong debug capabilities
• Experienced with SystemVerilog/UVM testbench development for complex SoCs Including GLS & SDF verifications
• Advanced scripting skills (Python, Perl, etc.) for automation and testbench infrastructure
• Deep knowledge of digital design, RTL design, and verification flows
• Strong troubleshooting and analytical debugging skills with ability to debug without logs
•  Ability to quickly adapt to complex infrastructure environments
•  Excellent hands-on debug skills and attention to detail
• Proficient in debugging firmware and RTL code using simulation tools  
• Exposure to leadership or mentorship is an asset 

 

 

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

#LI-PM2

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

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