SMTS Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SOC PD - Front End Integration (FEINT) Lead THE ROLE: The scoping of SOC PD FEINT (Front End Integration) lead includes Synthesis, Logic Equivalence, low power check, Timing Closure and full-chip SDC (constraints) generation. AMD design is big and complex with advanced process and technology. FEINT lead needs to have rich experience in each domain, control execution risk and lead the team to do high quality release on schedule. The lead needs to co-work with IP/DFT/PD teams, highlights critical issues and makes decisions to make project execution smoothly. THE PERSON: 13+ years working experience on ASIC Implementation Knowledgeable in all aspects of ASIC design flow Familiar with FEINT EDA tools Good leadership skills Good teamwork and script skills Good training skills to ramp-up new team members KEY RESPONSIBILITIES: Own full-chip / sub-system / partition level Synthesis, Equivalence checking and low power checks/signoff Co-work with IP/DFT/PD team to improve timing/area/power during synthesize Netlist quality check including EQV/LowPower/Timing Generate full-chip level SDC and SDC quality check Do working assignment for team members, tracking and supporting for critical problems Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective. Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects. Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology. PREFERRED EXPERIENCE: Synthesize experience by DC/DC-NXT/Fusion-Compiler EQV debug experience by FM/LEC Low power check experience by VC-LP Static Timing Analysis experience by PT Experience in STA, constraints, timing signoff and physical design Power Analysis experience by PTPX Good at scripts, like Python/perl/Tcl/Shell Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Master’s in Electronics/Electrical/Computer Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SOC PD - Front End Integration (FEINT) Lead THE ROLE: The scoping of SOC PD FEINT (Front End Integration) lead includes Synthesis, Logic Equivalence, low power check, Timing Closure and full-chip SDC (constraints) generation. AMD design is big and complex with advanced process and technology. FEINT lead needs to have rich experience in each domain, control execution risk and lead the team to do high quality release on schedule. The lead needs to co-work with IP/DFT/PD teams, highlights critical issues and makes decisions to make project execution smoothly. THE PERSON: 13+ years working experience on ASIC Implementation Knowledgeable in all aspects of ASIC design flow Familiar with FEINT EDA tools Good leadership skills Good teamwork and script skills Good training skills to ramp-up new team members KEY RESPONSIBILITIES: Own full-chip / sub-system / partition level Synthesis, Equivalence checking and low power checks/signoff Co-work with IP/DFT/PD team to improve timing/area/power during synthesize Netlist quality check including EQV/LowPower/Timing Generate full-chip level SDC and SDC quality check Do working assignment for team members, tracking and supporting for critical problems Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective. Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects. Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology. PREFERRED EXPERIENCE: Synthesize experience by DC/DC-NXT/Fusion-Compiler EQV debug experience by FM/LEC Low power check experience by VC-LP Static Timing Analysis experience by PT Experience in STA, constraints, timing signoff and physical design Power Analysis experience by PTPX Good at scripts, like Python/perl/Tcl/Shell Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Master’s in Electronics/Electrical/Computer Engineering #LI-SR4

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Tags: Yes, INR ₹4,293,240.00/Yr., INR ₹6,133,200.00/Yr., Global Careers (do not use for US or Canada)