SMTS Silicon Design Engineer (AECG ASIC DFx Lead)

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: AECG ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology. Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS. Writing and maintain DFT documentation and specifications. Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 12 years of DFT design, integration, verification, ATPG and Silicon Debug experience. Demonstrated technical leadership and works well with cross-functional teams. Excellent communication and interpersonal skills Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Experience in solving logic design or timing issues with integration, synthesis and PD teams. Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis. Knowledge of ATE and digital IC manufacturing test is a plus. Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in electrical/Electronic Engineering LOCATION: Penang, Malaysia #LI-MM1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: AECG ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology. Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS. Writing and maintain DFT documentation and specifications. Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 12 years of DFT design, integration, verification, ATPG and Silicon Debug experience. Demonstrated technical leadership and works well with cross-functional teams. Excellent communication and interpersonal skills Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Experience in solving logic design or timing issues with integration, synthesis and PD teams. Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis. Knowledge of ATE and digital IC manufacturing test is a plus. Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in electrical/Electronic Engineering LOCATION: Penang, Malaysia #LI-MM1 #LI-Hybrid

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Tags: No, MYR RM164,500.00/Yr., MYR RM235,000.00/Yr., Global Careers (do not use for US or Canada)