AMD

Physical Design Lead

Bangalore, India
USD 5k - 7k
Bash C++ Python Shell SQL API Docker Git Kubernetes AWS Azure GCP Linux Unix Windows Synopsys Mentor Graphics Fusion Compiler PrimeTime CalibreDRV UPF
Description
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Circuit Technology IP PD team, you will help bring to life cutting-edge designs. As a member of the Physical Design team, you will work closely with the PD Engineers, IP lead(Analog), RTL team, Verification team, ATPG team to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior & junior design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: End‑to‑end ownership of Synthesis‑to‑GDS flows for multiple PLL IPs Collaborate with IP leads to understand and translate design requirements Work with the RTL team to refine and validate SDC constraints Coordinate with the ATPG team for scan insertion activities Ownership of LEC, STA, Physical Verification, and all associated sign‑off checks Partner with SoC teams to resolve feedback (if any) after IP integration Work with CAD teams to address and resolve flow‑related issues PREFERRED EXPERIENCE: 12+ years Experience in the IP team. Experience with Synopys & Mentor tool. Fusion Compiler, PrimeTime, CalibreDRV. Multi-voltage design experience - UPF based designs. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Circuit Technology IP PD team, you will help bring to life cutting-edge designs. As a member of the Physical Design team, you will work closely with the PD Engineers, IP lead(Analog), RTL team, Verification team, ATPG team to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior & junior design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: End‑to‑end ownership of Synthesis‑to‑GDS flows for multiple PLL IPs Collaborate with IP leads to understand and translate design requirements Work with the RTL team to refine and validate SDC constraints Coordinate with the ATPG team for scan insertion activities Ownership of LEC, STA, Physical Verification, and all associated sign‑off checks Partner with SoC teams to resolve feedback (if any) after IP integration Work with CAD teams to address and resolve flow‑related issues PREFERRED EXPERIENCE: 12+ years Experience in the IP team. Experience with Synopys & Mentor tool. Fusion Compiler, PrimeTime, CalibreDRV. Multi-voltage design experience - UPF based designs. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PM2

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Tags: No, INR ₹4,686,640.00/Yr., INR ₹6,695,200.00/Yr., Global Careers (do not use for US or Canada)
AMD
AMD

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