Physical Design Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

 

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

PHYSICAL DESIGN ENGINEER 

 

#The Role:

We are looking for a motivated and detail-oriented **Physical Design Library Engineer** to join our VLSI backend team. This role sits at the intersection of **library management using CAD supported tools, and AI-driven automation** — playing a critical enabling function for Front End & Back End team.

 

You will own the end-to-end library delivery pipeline — from lib generation to tile owner unblocking — and will actively leverage and develop **AI-powered tools and dashboards** to improve team efficiency and visibility.

 

# Key Responsibilities:

Having 4+Years of experience in Physical Design

#Library Flow Ownership
- Own and execute the **LibBuilder flow** for standard cell and memory library generation
- Drive **MemView generation** for memory compiler outputs across multiple PVT corners and process nodes
- Maintain library quality and consistency across **NDM, Liberty (.lib), LEF, and timing model** deliverables
- Track and manage **PVT corner coverage** — ensure all required corners (SS, FF, TT, low voltage, high temperature) are generated and validated

 

# Cross-Team Coordination
- Serve as the primary point of contact for **library-related issues** raised by tile and block owners
- Proactively follow up with **internal teams** (design, DFT, timing) and **external teams** (foundry, IP vendors, memory compiler vendors) to resolve library blockers
- Unblock tile owners on **NDM / PVT mismatch issues** — diagnose root cause, coordinate fix, and validate resolution
- Coordinate with **CAD team** to ensure the latest compiler versions, EDA tool updates, and flow scripts are adopted in a timely manner

 

# Debug and Issue Resolution
- Perform **basic to intermediate debug** of library generation failures — identify issues in lib characterization, corner mapping, or MemView configuration
- Triage and escalate complex issues to the right teams with clear problem statements and reproduction steps
- Maintain a **library issue tracker** — log, prioritize, and close issues with documented root cause and fix

 

#AI Tools and Dashboard Development
- Comfortable working with **AI-assisted tools** (Genie, Claude Code, Copilot) for day-to-day productivity — querying, scripting, and automation
- Develop, enhance, and maintain **AI-generated dashboards** for library health, flow status, and PVT coverage visibility
- Proactively identify opportunities to **automate repetitive library tasks** using AI and scripting

 

## Knowledge of Physical Design Concepts

 -Timing concepts

-Different file formats, lef/def/oasis

• Education: Bachelor’s or master’s degree in related discipline preferred

 

#LI-SR5

Benefits offered are described: AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

PHYSICAL DESIGN ENGINEER 

 

#The Role:

We are looking for a motivated and detail-oriented **Physical Design Library Engineer** to join our VLSI backend team. This role sits at the intersection of **library management using CAD supported tools, and AI-driven automation** — playing a critical enabling function for Front End & Back End team.

 

You will own the end-to-end library delivery pipeline — from lib generation to tile owner unblocking — and will actively leverage and develop **AI-powered tools and dashboards** to improve team efficiency and visibility.

 

# Key Responsibilities:

Having 4+Years of experience in Physical Design

#Library Flow Ownership
- Own and execute the **LibBuilder flow** for standard cell and memory library generation
- Drive **MemView generation** for memory compiler outputs across multiple PVT corners and process nodes
- Maintain library quality and consistency across **NDM, Liberty (.lib), LEF, and timing model** deliverables
- Track and manage **PVT corner coverage** — ensure all required corners (SS, FF, TT, low voltage, high temperature) are generated and validated

 

# Cross-Team Coordination
- Serve as the primary point of contact for **library-related issues** raised by tile and block owners
- Proactively follow up with **internal teams** (design, DFT, timing) and **external teams** (foundry, IP vendors, memory compiler vendors) to resolve library blockers
- Unblock tile owners on **NDM / PVT mismatch issues** — diagnose root cause, coordinate fix, and validate resolution
- Coordinate with **CAD team** to ensure the latest compiler versions, EDA tool updates, and flow scripts are adopted in a timely manner

 

# Debug and Issue Resolution
- Perform **basic to intermediate debug** of library generation failures — identify issues in lib characterization, corner mapping, or MemView configuration
- Triage and escalate complex issues to the right teams with clear problem statements and reproduction steps
- Maintain a **library issue tracker** — log, prioritize, and close issues with documented root cause and fix

 

#AI Tools and Dashboard Development
- Comfortable working with **AI-assisted tools** (Genie, Claude Code, Copilot) for day-to-day productivity — querying, scripting, and automation
- Develop, enhance, and maintain **AI-generated dashboards** for library health, flow status, and PVT coverage visibility
- Proactively identify opportunities to **automate repetitive library tasks** using AI and scripting

 

## Knowledge of Physical Design Concepts

 -Timing concepts

-Different file formats, lef/def/oasis

• Education: Bachelor’s or master’s degree in related discipline preferred

 

#LI-SR5

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

Tags: No, INR ₹2,186,520.00/Yr., INR ₹3,123,600.00/Yr., Global Careers (do not use for US or Canada)