Memory IO DFT Architect & Silicon Validation Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: The Memory IO team is looking for a passionate and experienced PHY DFT Architecture & System/Silicon Validation Lead for the development of high-speed LPDDR, DDR and inter-chip IO IPs. Be a part of the definition, design and development and productization phase of industry-leading Memory PHYs and interface IP. This opportunity includes enabling & validation of new PHY designs at the microarchitecture, firmware/hardware/system co-design, and algorithm design level. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit and architecture teams develop leading edge Memory interfaces. THE PERSON: Have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, leader, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills KEY RESPONSIBILITIES: Lead and define PHY specific Design for Testing Features Define and drive PHY Silicon and System Validation Test Plans, Test Sequence creation, GUI/Flow development, & Quality Control. Coordinate & Enable IP Testing Readiness across R&D, Labs, IP Characterization, ESD testing, Unit & High Volume Testing, Board/system Design, SOCs and DRAM vendors. Work closely with firmware and BIOs team to drive post-silicon algorithm optimization and tuning Lead post-silicon training enhancements & validation to enable robust links for higher reliability / higher frequency margin Drive post-silicon execution across all stake holders and quality signoff. Being the front face of PHY supporting SOC, System, Testing Community and Customer Support PREFERRED EXPERIENCE: Excellent knowledge of C, C++ and any scripting language; knowledge of Verilog, Python and IP firmware is preferred Ability to adapt learn new toolsets and frameworks is required Post-silicon experience on real hardware is required. Experience with DDR, LPDDR, Memory Controller, or MAC Design experience is preferred Strong understanding of computer organization/architecture, memory IO sub-system, and system level HW/SW/DRAM/DIMM related to memory interface. Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc. Experience in leading IP through High Volume Manufacturing Testing, System Bring-Up & Product Launch Experience with PHY low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.) Knowledge of SIPI, Board design, JEDEC/DFI standard, and DRAM operations are strong plus. ACADEMIC CREDENTIALS: Bachelor's degree in Electrical or Computer engineering is required. Master's or PhD degree is a plus. LOCATION: Boxborough MA, Markham ON, Vancouver BC, Folsom CA, Austin TX, Santa Clara CA #LI-SL3 #LI-HYBRID At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: The Memory IO team is looking for a passionate and experienced PHY DFT Architecture & System/Silicon Validation Lead for the development of high-speed LPDDR, DDR and inter-chip IO IPs. Be a part of the definition, design and development and productization phase of industry-leading Memory PHYs and interface IP. This opportunity includes enabling & validation of new PHY designs at the microarchitecture, firmware/hardware/system co-design, and algorithm design level. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit and architecture teams develop leading edge Memory interfaces. THE PERSON: Have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, leader, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills KEY RESPONSIBILITIES: Lead and define PHY specific Design for Testing Features Define and drive PHY Silicon and System Validation Test Plans, Test Sequence creation, GUI/Flow development, & Quality Control. Coordinate & Enable IP Testing Readiness across R&D, Labs, IP Characterization, ESD testing, Unit & High Volume Testing, Board/system Design, SOCs and DRAM vendors. Work closely with firmware and BIOs team to drive post-silicon algorithm optimization and tuning Lead post-silicon training enhancements & validation to enable robust links for higher reliability / higher frequency margin Drive post-silicon execution across all stake holders and quality signoff. Being the front face of PHY supporting SOC, System, Testing Community and Customer Support PREFERRED EXPERIENCE: Excellent knowledge of C, C++ and any scripting language; knowledge of Verilog, Python and IP firmware is preferred Ability to adapt learn new toolsets and frameworks is required Post-silicon experience on real hardware is required. Experience with DDR, LPDDR, Memory Controller, or MAC Design experience is preferred Strong understanding of computer organization/architecture, memory IO sub-system, and system level HW/SW/DRAM/DIMM related to memory interface. Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc. Experience in leading IP through High Volume Manufacturing Testing, System Bring-Up & Product Launch Experience with PHY low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.) Knowledge of SIPI, Board design, JEDEC/DFI standard, and DRAM operations are strong plus. ACADEMIC CREDENTIALS: Bachelor's degree in Electrical or Computer engineering is required. Master's or PhD degree is a plus. LOCATION: Boxborough MA, Markham ON, Vancouver BC, Folsom CA, Austin TX, Santa Clara CA #LI-SL3 #LI-HYBRID

At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Tags: No, USD $155,260.00/Yr., USD $221,800.00/Yr., US Careers (External)