Manager Silicon Design Engineering

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Silicon Design Verification Manager The role: A Design Verification Manager role in our Security IP (SECIP) development team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. As a hands-on verification manager, you will lead a number of verification engineers and work on block level functional verification and its closure, and on subsystem level integration and verification for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications. The person: An experienced hardware/firmware co-design/verification leader with strong records of technical leadership and hands-on execution to meet block level IP and MP subsystems design and verification project milestones. A technical mentor and forward-thinking leader who demonstrated strong capability in establishing advanced design verification methodology and workflow, anticipating/analyzing/resolving technical and planning issues, and enjoyed interacting with team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. Key responsibilities: Develop block level IP and MP subsystem verification testbench architecture, test methodology, and automated verification infrastructure Lead development and debugging of functional models and test plans using SystemVerilog/UVM constrained-random test methodology and C-DPI directed test methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests Manage regression result triaging, test debug, and coverage analysis, and resolve technical issues with design, verification, and other teams, to improve verification metrics Participate in subsystem specification, influence IP micro-architecture development (design for verification aspect), apply reusable test methodology across individual IP and MP subsystems Coordinate resolution of IP integration issues with SoC Integration, SoC DV and post-silicon validation teams Collaborate with project management and other team leads on verification delivery against the project milestone requirements and verification metrics Collaborate with other technical leads on process, methodology, and technical enhancements to design verification, to drive continuous improvement and positive changes Preferred experience: A minimum of equivalent 10 years relevant experience in RTL design verification. Proven experience in verifying commercially successful IP and subsystems Demonstrated understanding of IP and MP subsystem architecture and of FPGA based simulation or emulation methodology Proficient in SystemVerilog, Verilog (an extra asset), object-oriented programming, and scripting (using Ruby, Perl, Python and Makefile) Deep knowledge about state-of-art verification methodology and best practices such as UVM and C-DPI Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA) Excellent experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc. Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, a positive influencer on team morale and culture Prior technical management experience is a plus asset Academic credentials: Major in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field Master's or PhD Degree preferred #LI-PL1 #LI-HYBRID #SECIPSerbia Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Silicon Design Verification Manager The role: A Design Verification Manager role in our Security IP (SECIP) development team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. As a hands-on verification manager, you will lead a number of verification engineers and work on block level functional verification and its closure, and on subsystem level integration and verification for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications. The person: An experienced hardware/firmware co-design/verification leader with strong records of technical leadership and hands-on execution to meet block level IP and MP subsystems design and verification project milestones. A technical mentor and forward-thinking leader who demonstrated strong capability in establishing advanced design verification methodology and workflow, anticipating/analyzing/resolving technical and planning issues, and enjoyed interacting with team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. Key responsibilities: Develop block level IP and MP subsystem verification testbench architecture, test methodology, and automated verification infrastructure Lead development and debugging of functional models and test plans using SystemVerilog/UVM constrained-random test methodology and C-DPI directed test methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests Manage regression result triaging, test debug, and coverage analysis, and resolve technical issues with design, verification, and other teams, to improve verification metrics Participate in subsystem specification, influence IP micro-architecture development (design for verification aspect), apply reusable test methodology across individual IP and MP subsystems Coordinate resolution of IP integration issues with SoC Integration, SoC DV and post-silicon validation teams Collaborate with project management and other team leads on verification delivery against the project milestone requirements and verification metrics Collaborate with other technical leads on process, methodology, and technical enhancements to design verification, to drive continuous improvement and positive changes Preferred experience: A minimum of equivalent 10 years relevant experience in RTL design verification. Proven experience in verifying commercially successful IP and subsystems Demonstrated understanding of IP and MP subsystem architecture and of FPGA based simulation or emulation methodology Proficient in SystemVerilog, Verilog (an extra asset), object-oriented programming, and scripting (using Ruby, Perl, Python and Makefile) Deep knowledge about state-of-art verification methodology and best practices such as UVM and C-DPI Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA) Excellent experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc. Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, a positive influencer on team morale and culture Prior technical management experience is a plus asset Academic credentials: Major in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field Master's or PhD Degree preferred #LI-PL1 #LI-HYBRID #SECIPSerbia

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Tags: No, RSD RSD5,530,000.00/Yr., RSD RSD7,900,000.00/Yr., Global Careers (do not use for US or Canada)