Lead SoC / IP Formal Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SILICON DESIGN ENGINEER    THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Formal Verificaion Signoff convergence team , you will work closely with the architecture, RTL and physical design teams to achieve first pass silicon success.   THE PERSON:  A successful candidate will work on full chip SoC formal verification convergence with RTL and physical design engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills.   KEY RESPONSIBILITIES:  Work on full chip Formal Verifcation on multiple ASICs across different technology nodes. Work closely with architecture, RTL and Physical Design team to ensure robust design Work witih RTL and PD team on Conformal ECO generation to reduce TAT Work closely with CAD team to come up with new flows and methodologies in the FV domain PREFERRED EXPERIENCE:  7+ years of professional experience in the industry in formal verification Proficient in IP and Full Chip Formal Verification Proficient in debugging issues related to formal verification Handson expericene in Cadence LEC/Synospsy Formality Working knowledge of Conformal ECO generation methodology Automating workflows in a distributed compute environment.   Scripting language experience: Perl, Tcl, Makefile, shell preferred.   Exposure to leadership or mentorship is an asset   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

MTS SILICON DESIGN ENGINEER    THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Formal Verificaion Signoff convergence team , you will work closely with the architecture, RTL and physical design teams to achieve first pass silicon success.   THE PERSON:  A successful candidate will work on full chip SoC formal verification convergence with RTL and physical design engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills.   KEY RESPONSIBILITIES:  Work on full chip Formal Verifcation on multiple ASICs across different technology nodes. Work closely with architecture, RTL and Physical Design team to ensure robust design Work witih RTL and PD team on Conformal ECO generation to reduce TAT Work closely with CAD team to come up with new flows and methodologies in the FV domain PREFERRED EXPERIENCE:  7+ years of professional experience in the industry in formal verification Proficient in IP and Full Chip Formal Verification Proficient in debugging issues related to formal verification Handson expericene in Cadence LEC/Synospsy Formality Working knowledge of Conformal ECO generation methodology Automating workflows in a distributed compute environment.   Scripting language experience: Perl, Tcl, Makefile, shell preferred.   Exposure to leadership or mentorship is an asset   ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Tags: No, INR ₹3,235,890.00/Yr., INR ₹4,622,700.00/Yr., Global Careers (do not use for US or Canada)