Lead Physical Design Engineer, Place & Route

ADVANCE YOUR CAREER. ADVANCE THE WORLD. 

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. 

 

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

 

THE ROLE:

 

THE PERSON:

 

KEY RESPONSIBLITIES:

• Lead place-and-route execution from floorplanning through signoff.
• Drive timing, congestion, and power closure for complex designs.
• Develop and optimize floorplanning, placement, clock tree, and routing strategies.
• Identify and resolve critical physical design and implementation issues.
• Perform timing analysis, parasitic extraction, and power integrity analysis.
• Execute physical verification and signoff activities, including ERC and LVS.
• Provide technical guidance and drive implementation quality across design activities.
• Partner with architecture, design, integration, and product engineering teams to deliver successful silicon.
• Enhance physical design methodologies, automation, and implementation flows.

PREFERRED EXPERIENCE:

• Experience with ASIC physical design and implementation flows.
• Strong expertise in place-and-route methodologies for complex designs.
• Experience with floorplanning, placement, clock tree synthesis, routing, and timing closure.
• Experience resolving timing, congestion, power, and signal integrity challenges.
• Experience with physical verification and signoff methodologies, including ERC and LVS.
• Experience with advanced-node and high-speed design implementations.
• Proficiency with Synopsys Fusion Compiler, Cadence, and Siemens EDA tools.
• Experience with TCL, Perl, or Shell scripting for design automation and flow development.
• Experience providing technical leadership across physical design activities.

 

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field preferred.

 

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Benefits offered are described: AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

 

THE ROLE:

 

THE PERSON:

 

KEY RESPONSIBLITIES:

• Lead place-and-route execution from floorplanning through signoff.
• Drive timing, congestion, and power closure for complex designs.
• Develop and optimize floorplanning, placement, clock tree, and routing strategies.
• Identify and resolve critical physical design and implementation issues.
• Perform timing analysis, parasitic extraction, and power integrity analysis.
• Execute physical verification and signoff activities, including ERC and LVS.
• Provide technical guidance and drive implementation quality across design activities.
• Partner with architecture, design, integration, and product engineering teams to deliver successful silicon.
• Enhance physical design methodologies, automation, and implementation flows.

PREFERRED EXPERIENCE:

• Experience with ASIC physical design and implementation flows.
• Strong expertise in place-and-route methodologies for complex designs.
• Experience with floorplanning, placement, clock tree synthesis, routing, and timing closure.
• Experience resolving timing, congestion, power, and signal integrity challenges.
• Experience with physical verification and signoff methodologies, including ERC and LVS.
• Experience with advanced-node and high-speed design implementations.
• Proficiency with Synopsys Fusion Compiler, Cadence, and Siemens EDA tools.
• Experience with TCL, Perl, or Shell scripting for design automation and flow development.
• Experience providing technical leadership across physical design activities.

 

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field preferred.

 

#LI-LC3

#LI-HYBRID

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

Tags: No, CAD $135,800.00/Yr., CAD $194,000.00/Yr., Canada Careers (External)