Staff HSIO DFT Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS - HSIO DFT Design Verification Engineer MTS SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivated DFT design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The NBIO DFx team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: Will have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Design verification of PCIe, UCIe, Chiplet Interconnect IPs for Analog/HSIO DFx features Build testbench components to support the next generation of NBIO IPs Estimate the time required to write the new feature tests and any required changes to the test environment Develop, maintain, and improve test libraries to support IP level testing Test coverage and test cost reduction analysis Train and mentor junior team members for PRBS DV execution Provide technical support to SoC and Post-Si teams to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of Design for Test methodologies and DFT verification experience (e.g. JTAG 1149.x, IJTAG, PRBS, IO Loopback, etc.) Experienced with Verilog, System Verilog, C, and C++ Developing UVM based verification frameworks and testbenches, processes and flows Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design Debug test failures to determine the root cause; work with design engineers to resolve design defects and correct any test issues Experience with ATE (Automatic Test Equipment) - ATE test pattern & test flow development, debug, test and characterization Design verification experience of High-Speed IO PHY and Controller logic is preferred ACADEMIC CREDENTIALS: Bachelor’s or master’s degree in related discipline preferred #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

MTS - HSIO DFT Design Verification Engineer MTS SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivated DFT design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The NBIO DFx team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: Will have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Design verification of PCIe, UCIe, Chiplet Interconnect IPs for Analog/HSIO DFx features Build testbench components to support the next generation of NBIO IPs Estimate the time required to write the new feature tests and any required changes to the test environment Develop, maintain, and improve test libraries to support IP level testing Test coverage and test cost reduction analysis Train and mentor junior team members for PRBS DV execution Provide technical support to SoC and Post-Si teams to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of Design for Test methodologies and DFT verification experience (e.g. JTAG 1149.x, IJTAG, PRBS, IO Loopback, etc.) Experienced with Verilog, System Verilog, C, and C++ Developing UVM based verification frameworks and testbenches, processes and flows Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design Debug test failures to determine the root cause; work with design engineers to resolve design defects and correct any test issues Experience with ATE (Automatic Test Equipment) - ATE test pattern & test flow development, debug, test and characterization Design verification experience of High-Speed IO PHY and Controller logic is preferred ACADEMIC CREDENTIALS: Bachelor’s or master’s degree in related discipline preferred #LI-PM2

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Tags: No, INR ₹3,235,890.00/Yr., INR ₹4,622,700.00/Yr., Global Careers (do not use for US or Canada)