DFT DV Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

 

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

 

 

The successful candidate will own the DFX design, develop and implement cutting edge DFX features including SSN, EDT, ATPG etc. Work closely with the DFX Architecture and Design teams and SoC teams to align on the DFX requirements and successfully implement and verify the DFX features, find creative ways to accelerate the existing process.

PREFERRED EXPERIENCE: 
Experience and understanding of ASIC DFX, SSN Architecture, EDT Architecture, ATPG experience in tile and SoC (die and package) level experience. Expertise in writing custom ICL and PDL.

Applicant should be familiar with scan hardware compressions, failure mechanisms, and debug processes. 
IJTAG/ IEEE 1687: Utilizing IJTAG infrastructure to configure SSN, create instrument connectivity language (ICL) models, and develop Procedural Description Language (PDL) commands to manage test instruments.

Familiar in ICL Extraction & PDL Retargeting, from RTL/Gate Netlist to describe instrumentation and retargeting PDL commands from the IP level to the top level. EDT, SSN and SSH architecture understanding, IJTAG,EDT, TestKompress, simulation and verification flow and experience of working in DFX architecture of complex SOC Patterns re-targeting. Spyglass Experience with RTL quality check tools/methodologies such as Spyglass, Lint is required.

 

DFX/DV - Design for Testability/Verification: Verifying SSN and Scan architectures using gate-level simulations, SCAN architecture, TAP/JTAG related DV feature, and validating patterns. Integrating test bench with sv based test bench.

Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem Experience in End-to-End DFX flow development/creation. Expert in at least one of the scripting tool (Perl, Python, TCL) and ability to create complex flows/scripts that provide scalable solutions to DFX implementation. 

Strong EDA tools experience Tessent - Testkompress, SSN, IJTAG, EDT. Scan/ATPG patterns & test flows development, debug, test, and characterization Excellent hands-on debug skills and scripting skills are critical.

Strong communication skills and the ability to collaborate effectively within a global team environment are essential. Strong problem-solving skills Knowledge.

 

 

Good to have experience:

• Hands on verification experience with C/C++/SystemVerilog/UVM testbench development.

 

 

ACADEMIC CREDENTIALS:

• Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering

 

LOCATION: Bangalore, India

 

This team is vital to the success of AMD as a growing company. It is a dynamic and exciting ASIC design environment. You will be working on some of the most exciting projects with leading edge technologies

• #LI-BM2 

Benefits offered are described: AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

 

 

The successful candidate will own the DFX design, develop and implement cutting edge DFX features including SSN, EDT, ATPG etc. Work closely with the DFX Architecture and Design teams and SoC teams to align on the DFX requirements and successfully implement and verify the DFX features, find creative ways to accelerate the existing process.

PREFERRED EXPERIENCE: 
Experience and understanding of ASIC DFX,  SSN Architecture, EDT Architecture,  ATPG experience in tile and SoC (die and package) level experience.  Expertise in writing custom ICL and PDL.

Applicant should be familiar with scan hardware compressions, failure mechanisms, and debug processes. 
IJTAG/ IEEE 1687: Utilizing IJTAG infrastructure to configure SSN, create instrument connectivity language (ICL) models, and develop Procedural Description Language (PDL) commands to manage test instruments.

Familiar in ICL Extraction & PDL Retargeting, from RTL/Gate Netlist to describe instrumentation and retargeting PDL commands from the IP level to the top level. EDT, SSN and SSH architecture understanding, IJTAG,EDT, TestKompress, simulation and verification flow and experience of working in DFX architecture of complex SOC Patterns re-targeting. Spyglass Experience with RTL quality check tools/methodologies such as Spyglass, Lint is required.

 

DFX/DV - Design for Testability/Verification: Verifying SSN and Scan architectures using gate-level simulations,  SCAN architecture, TAP/JTAG related DV feature, and validating patterns. Integrating test bench with sv based test bench.

Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem Experience in End-to-End DFX flow development/creation.  Expert in at least one of the scripting tool (Perl, Python, TCL) and ability to create complex flows/scripts that provide scalable solutions to DFX implementation. 

Strong EDA tools experience Tessent - Testkompress, SSN, IJTAG, EDT.  Scan/ATPG patterns & test flows development, debug, test, and characterization Excellent hands-on debug skills and scripting skills are critical.

Strong communication skills and the ability to collaborate effectively within a global team environment are essential. Strong problem-solving skills Knowledge.

 

 

Good to have experience:

• Hands on verification experience with C/C++/SystemVerilog/UVM testbench development.

 

 

ACADEMIC CREDENTIALS:

• Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering

 

LOCATION: Bangalore, India

 

This team is vital to the success of AMD as a growing company. It is a dynamic and exciting ASIC design environment.  You will be working on some of the most exciting projects with leading edge technologies

• #LI-BM2 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

Tags: No, INR ₹3,338,160.00/Yr., INR ₹4,768,800.00/Yr., Global Careers (do not use for US or Canada)