DFT Architect

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE: Circuit Technology team is looking for a passionate and experienced DFT Methodology/Architect/RTL execution Lead for the high-speed SERDES Phys, Next gen Memory Phys and Die-to-Die interconnect IPs. This opportunity includes ownership of defining the DFX architecture for high-speed PHYs as well as die-to die connectivity IP designs, RTL coding, supporting scan stitching, timing constraints development, supporting ATPG as well as post-silicon bringup. Be a part of a team that delivers Industry leading IPs that touch every single SOC delivered by AMD. The Person Have strong analytical/problem-solving skills and pronounced attention to details. Must be able to execute hands-on, a self-starter, a leader, and be able to independently drive tasks to completion. Key Responsiblities Lead and define PHY specific Design for Test/Debug/Yield Features. Implementation of DFX features into RTL using verilog. Understanding of DFX Architectures and micro-architectures. Experience with JTAG (1149.1/1687/1500)/IJTAG, Scan Compression (EDT, SSH), and at-speed scan testing implementation. Gate level simulation using Synopsys VCS and Verdi. Spyglass bringup and analysis for scan readiness/test coverage gaps. MBIST planning, implementation, and verification. Support Test Engineering on planning, patterns, and debug. Support silicon bring-up and debug. Develop efficient DFx flows and methodology compatible with front end and physical design flows. Preferred Experience Experience with industry standard ATPG and DFx insertion CAD tools. Familiarity with industry standard DFX methodology: e.g Streaming Scan Network (aka SSN), IJTAG, ICL/PDL etc Familiarity with SystemVerilog and UVM. Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors. Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling. Good understanding of high-performance, low-power design fundamentals. Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. Exposure to post-silicon testing and tester pattern debug are major assets. Strong problem solving and debug skills across various levels of design hierarchies. Academic Credentials BS/MS/PhD in EE/ECE/CE/CS with industry experience in advanced DFx techniques. #LI-PM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

SMTS SILICON DESIGN ENGINEER THE ROLE: Circuit Technology team is looking for a passionate and experienced DFT Methodology/Architect/RTL execution Lead for the high-speed SERDES Phys, Next gen Memory Phys and Die-to-Die interconnect IPs. This opportunity includes ownership of defining the DFX architecture for high-speed PHYs as well as die-to die connectivity IP designs, RTL coding, supporting scan stitching, timing constraints development, supporting ATPG as well as post-silicon bringup. Be a part of a team that delivers Industry leading IPs that touch every single SOC delivered by AMD. The Person Have strong analytical/problem-solving skills and pronounced attention to details. Must be able to execute hands-on, a self-starter, a leader, and be able to independently drive tasks to completion. Key Responsiblities Lead and define PHY specific Design for Test/Debug/Yield Features. Implementation of DFX features into RTL using verilog. Understanding of DFX Architectures and micro-architectures. Experience with JTAG (1149.1/1687/1500)/IJTAG, Scan Compression (EDT, SSH), and at-speed scan testing implementation. Gate level simulation using Synopsys VCS and Verdi. Spyglass bringup and analysis for scan readiness/test coverage gaps. MBIST planning, implementation, and verification. Support Test Engineering on planning, patterns, and debug. Support silicon bring-up and debug. Develop efficient DFx flows and methodology compatible with front end and physical design flows. Preferred Experience Experience with industry standard ATPG and DFx insertion CAD tools. Familiarity with industry standard DFX methodology: e.g Streaming Scan Network (aka SSN), IJTAG, ICL/PDL etc Familiarity with SystemVerilog and UVM. Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors. Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling. Good understanding of high-performance, low-power design fundamentals. Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. Exposure to post-silicon testing and tester pattern debug are major assets. Strong problem solving and debug skills across various levels of design hierarchies. Academic Credentials BS/MS/PhD in EE/ECE/CE/CS with industry experience in advanced DFx techniques. #LI-PM2

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Tags: No, INR ₹4,686,640.00/Yr., INR ₹6,695,200.00/Yr., Global Careers (do not use for US or Canada)