Design Verification - Tech Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ TITLE: Design Verification Lead THE ROLE: CIT team is a dynamic and innovative team dedicated to pushing boundaries of hardware development. We are seeking skilled and motivated verification engineer to join our growing team and contribute to the success of cutting-edge IPs. We are currently looking for experienced ASIC Design Verification engineer who will be involved in all aspects of design verification activities using the latest methodologies with the help of automation keeping power and performance in mind. The candidate will utilize/develop a variety of verification components using the latest verification methodology to achieve an excellent RTL/Firmware design quality. The CIT team designs AMD chiplet technology. The Design Verification group within this team is responsible for developing a scalable DV flow with new emphasis on automation, power, and performance. The NBIO organization has great diversity of talent across the globe. Our management fosters and encourages continuous technical innovation to show case successes and facilitate continuous career development. THE PERSON: Will demonstrate strong analytical thinking and problem solving skills with an excellent attention to detail. Will have good communication and writing skills, Will have good teamwork and interpersonal skills, RESPONSIBILITIES: · Lead existing verification team and scale current team for supporting future roadmap in chiplet interconnects across server, datacenter and AI accelerator product lines · Closely work with architects and designers to develop verification strategies and execution plans. · Participate in verification of complex IP blocks, take end to end ownership of key features for all projects. · Work on test plans, test case development, testbench enhancement, regression, and coverage closure. · Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification. · Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments. · Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in SystemVerilog/UVM. · Analyzing Functional, Code, and Test Plan Coverage. · Implementing Assertions, Checkers, and Monitors. · Triaging and Debugging Regressions. · Reproducing Functional Bugs found in Silicon, in Simulation and/or Formal Verification tools. · Conducting and participating in Code Reviews. PREFERRED EXPERIENCE & SKILL SETS: · At least 10+ years of extensive hardware verification experience. Leadership experience is strong plus. · Strong experience with verification of high-speed IO and interconnects like PCIe. Previous experience with chiplet interconnect is a strong plus. · Must be proficient in Verilog, System Verilog, UVM, and working in Linux and Windows environments · Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools · Must have excellent programming skills · Must have exposure to Makefile and other scripting languages like perl, python and ruby EDUCATION : Bachelors or Master’s Degree in Electrical Engineering or Computer Engineering #LI-PL1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

TITLE: Design Verification Lead THE ROLE: CIT team is a dynamic and innovative team dedicated to pushing boundaries of hardware development. We are seeking skilled and motivated verification engineer to join our growing team and contribute to the success of cutting-edge IPs. We are currently looking for experienced ASIC Design Verification engineer who will be involved in all aspects of design verification activities using the latest methodologies with the help of automation keeping power and performance in mind. The candidate will utilize/develop a variety of verification components using the latest verification methodology to achieve an excellent RTL/Firmware design quality. The CIT team designs AMD chiplet technology. The Design Verification group within this team is responsible for developing a scalable DV flow with new emphasis on automation, power, and performance. The NBIO organization has great diversity of talent across the globe. Our management fosters and encourages continuous technical innovation to show case successes and facilitate continuous career development. THE PERSON: Will demonstrate strong analytical thinking and problem solving skills with an excellent attention to detail. Will have good communication and writing skills, Will have good teamwork and interpersonal skills, RESPONSIBILITIES: · Lead existing verification team and scale current team for supporting future roadmap in chiplet interconnects across server, datacenter and AI accelerator product lines · Closely work with architects and designers to develop verification strategies and execution plans. · Participate in verification of complex IP blocks, take end to end ownership of key features for all projects. · Work on test plans, test case development, testbench enhancement, regression, and coverage closure. · Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification. · Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments. · Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in SystemVerilog/UVM. · Analyzing Functional, Code, and Test Plan Coverage. · Implementing Assertions, Checkers, and Monitors. · Triaging and Debugging Regressions. · Reproducing Functional Bugs found in Silicon, in Simulation and/or Formal Verification tools. · Conducting and participating in Code Reviews. PREFERRED EXPERIENCE & SKILL SETS: · At least 10+ years of extensive hardware verification experience. Leadership experience is strong plus. · Strong experience with verification of high-speed IO and interconnects like PCIe. Previous experience with chiplet interconnect is a strong plus. · Must be proficient in Verilog, System Verilog, UVM, and working in Linux and Windows environments · Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools · Must have excellent programming skills · Must have exposure to Makefile and other scripting languages like perl, python and ruby EDUCATION : Bachelors or Master’s Degree in Electrical Engineering or Computer Engineering #LI-PL1 #LI-HYBRID

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Tags: No, RSD RSD5,600,000.00/Yr., RSD RSD8,000,000.00/Yr., Global Careers (do not use for US or Canada)