DDR Functional Validation Engineer

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DDR Functional Validation Engineer

Role Summary

The DDR Functional Validation Engineer is responsible for end-to-end enablement, functional validation, and debug of the server memory subsystem, spanning UMC, DRAM, firmware, BIOS, platform, and system-level interactions. The role drives new DDR features from initial enablement through production readiness by developing validation strategies and test content, executing across representative hardware configurations, identifying silicon and firmware defects, and partnering with architecture, design, firmware, platform, and validation teams to drive issues to closure.

DDR FV's broader charter includes feature enablement, IP/unit-level validation, cross-feature and system-level validation, hardware/software breadth coverage, memory debug, AVL activities, memory-partner engagement, and BIOS regression validation.

Key Responsibilities

DDR Feature Validation

• Develop and execute DDR functional validation plans for new memory-controller and memory-subsystem capabilities.
• Translate architectural and design requirements into test plans, validation content, execution matrices, and measurable pass/fail criteria.
• Validate DDR features across relevant speeds, operating modes, memory configurations, BIOS/FW revisions, and server platforms.
• Exercise individual features as well as interactions with power management, RAS, training, refresh, and other system-level behaviors.
• Drive validation from initial enablement through feature sign-off and production readiness.

Silicon & System Debug

• Analyze validation failures and isolate issues across silicon/RTL, UMC, firmware, BIOS, DRAM, platform, and test-content boundaries.
• Use register data, logs, traces, reproduction experiments, configuration comparisons, and targeted stress scenarios to establish root cause.
• File and drive defects to resolution with design, architecture, firmware, and platform owners.
• Validate fixes and workarounds and close the loop by converting discoveries into stronger regression coverage.

 

LOCATION: 

Austin, TX

 

This role is not eligible for visa sponsorship.

 

#LI-DNI

Benefits offered are described: AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

DDR Functional Validation Engineer

Role Summary

The DDR Functional Validation Engineer is responsible for end-to-end enablement, functional validation, and debug of the server memory subsystem, spanning UMC, DRAM, firmware, BIOS, platform, and system-level interactions. The role drives new DDR features from initial enablement through production readiness by developing validation strategies and test content, executing across representative hardware configurations, identifying silicon and firmware defects, and partnering with architecture, design, firmware, platform, and validation teams to drive issues to closure.

DDR FV's broader charter includes feature enablement, IP/unit-level validation, cross-feature and system-level validation, hardware/software breadth coverage, memory debug, AVL activities, memory-partner engagement, and BIOS regression validation.

Key Responsibilities

DDR Feature Validation

• Develop and execute DDR functional validation plans for new memory-controller and memory-subsystem capabilities.
• Translate architectural and design requirements into test plans, validation content, execution matrices, and measurable pass/fail criteria.
• Validate DDR features across relevant speeds, operating modes, memory configurations, BIOS/FW revisions, and server platforms.
• Exercise individual features as well as interactions with power management, RAS, training, refresh, and other system-level behaviors.
• Drive validation from initial enablement through feature sign-off and production readiness.

Silicon & System Debug

• Analyze validation failures and isolate issues across silicon/RTL, UMC, firmware, BIOS, DRAM, platform, and test-content boundaries.
• Use register data, logs, traces, reproduction experiments, configuration comparisons, and targeted stress scenarios to establish root cause.
• File and drive defects to resolution with design, architecture, firmware, and platform owners.
• Validate fixes and workarounds and close the loop by converting discoveries into stronger regression coverage.

 

LOCATION: 

Austin, TX

 

This role is not eligible for visa sponsorship.

 

#LI-DNI

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.

Tags: No, USD $98,560.00/Yr., USD $140,800.00/Yr., US Careers (External)