Staff Engineer - Design Verification

Location: Singapore

Department: DV

Scope

You will be responsible for verifying digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, security hardware, and other logic for IoT applications.

Responsibilities

• The right candidate will be a self-starter who assumes full ownership of DV tasks and delivers high-quality results.
• Develop test plans at block, sub-system, and chip level.
• Execute SoC-based verification at full-chip and module level verification. 
• Experience in ARM or RISC-V based micro-controllers.
• Power-aware methodology (CPF/UPF).
• Write C-based lib packages and tests.
• Architect and implement scalable and reusable module test benches using SystemVerilog and UVM.
• Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.
• Automate the test environment for randomized testing and score-boarding.
• Utilize advanced debugging techniques to identify and resolve design and verification issues.
• Perform root-cause analysis and work with design teams to fix identified issues.
• Define and track functional and code coverage metrics to ensure thorough verification.
• Ensure that verification quality meets or exceeds industry standards and project requirements.
• Edge-based AI inference is preferred.

Qualifications

• BSEE/MSEE with 7 - 10+ years of experience (seniority depends on years of experience) in block, sub-system, and full-chip verification.
• Technologies: Experienced in ARM M/RISC-V (Preferred) SoC Verification, expert in AMBA AXI/AHB/APB, DMA, Flow Control, Serial Devices, Low Power (CPF/UPF) Verification, 3rd party IP integration verification.
• Experience in peripheral modules (UART, SPI, I2C), Audio subsystem, Display subsystem, USB, OTP, Crypto is a plus.
• Languages: Strong in SystemVerilog (UVM), Verilog, C/C++, Python, Perl, or Makefile.
• Should have delivered multiple chips functioning to specification.
• Identify and manage verification deliverables, milestones, and schedules.
• Proactively identify potential verification risks and develop mitigation strategies.
• Collaborate with design, architecture, and software teams to understand and verify design intent.
• Communicate verification progress, issues, and results to stakeholders and management.
• Strong in understanding multiple architectures, integrating 3rd party IPs/VIPs, and working with mixed-signal designs with low-power design and verification challenges.
• Strong understanding/exposure to Design Verification for low-power battery-operated designs is highly desired.
• C-based verification in an SoC environment is required.
• Experience with ARM processor-based designs and low-power design techniques is a plus.