Ambarella

VLSI Design Verification Engineer

Hsinchu, Taiwan
SystemVerilog UVM AI
Description

VLSI Design Verification Engineer

Location: Taiwan Hsinchu

Time Type: Full time

Job Description

AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

We are looking for talented engineers to join our VLSI Verification team. You’ll work on next-generation SoCs, applying advanced verification methodologies (SystemVerilog/UVM, coverage-driven, assertion-based) and leveraging AI-assisted tools to accelerate testplan writing, assertion development, and debug.

Responsibilities
• Develop and execute verification plans for complex SoCs/IPs
• Build testbenches, assertions, and coverage models
• Collaborate with architects, designers, and post-silicon teams
• Ensure correctness and reliability of cutting-edge designs

Why Join Us
• Cutting-edge verification with AI-powered flows
• Work alongside global world-class engineers
• Accelerated growth in a learning-driven culture
If you are smart, curious, and eager to learn, join us and shape the future of silicon innovation!

Ambarella
Ambarella

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