Sr. ASIC Implementation Engineer, DBF Silicon

• Bachelor's degree in Electrical / Communications Engineering or related field, or equivalent experience.
• 7+ years of experience in ASIC implementation, i.e., synthesis, STA and working with P&R for deep sub-micron nodes, preferably 16nm or smaller.
• Experience leading or solely developing the methodology and scripts for physical synthesis.
• Proven track record in taping out chips that have gone in to high volume production.
• Familiar with implementing chips that have multiple power islands and power gating.

• Master's or Ph.D degree in Electrical / Communications Engineering.
• 10+ years of experience in ASIC implementation.
• Experience in leading physical design.
• Strong exposure to UPF flow for low power design.
• Strong written and verbal skills
• Experience of working in multi-site/multi-team environment


Amazon is committed to a diverse and inclusive workplace. Amazon is an equal opportunity employer and does not discriminate on the basis of race, national origin, gender, gender identity, sexual orientation, protected veteran status, disability, age, or other legally protected status. For individuals with disabilities who would like to request an accommodation, please visit https://www.amazon.jobs/en/disability/us.

Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.

Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $143,300/year in our lowest geographic market up to $247,600/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit https://www.aboutamazon.com/workplace/employee-benefits. This position will remain posted until filled. Applicants should apply via our internal or external career site.
Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.

The Role:
Be part of Project Kuiper’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.

In this role you will:
• As the implementation lead you will set up the flow for both logic and physical synthesis flow for various technology nodes.
• Work with the ASIC design and DFT teams to understand the design and create timing constraints.
• Check the RTL design for clean synthesis run, perform STA and LEC on netlist.
• Work with RFIC teams to make sure the top level integration of analog blocks are done properly and correct by construction, including formal connectivity checks.
• Work with P&R teams to ensure a smooth hand off of netlists, ensure the timely execution of the P&R responsibilities by that team.
• Participate in flow reviews of all the blocks with the P&R team to ensure that they achieve the best PPA for all blocks.
• Lead the timing sign-off for the post P&R database.
• Ensure that the chip meets the required DFM criteria by verifying the IR/EM results.


Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.