Senior Verification Tech Lead

- Electrical/Computer Science engineer
- 8+ years of experience with full-chip/system-level verification of a large-scale SoC
- Experience with Test Writing and SW development (C/C++/Assembly)
- Hands-on verification/validation experience, including: debugging emulation and/or silicon platforms, waveform debugging, coverage definition and analysis, etc.
- Knowledge of ARM architecture
- Knowledge of the following programming languages: Perl/Bash/TCl/Python
- Knowledge of Processors, PCIe, Ethernet, DDR
- Knowledge of Hardware Verification concepts and tools (UVM , Coverage Driven verification), Verilog/SystemVerilog/Specman

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Annapurna Labs is the team behind AWS Graviton the industry's most advanced ARM-based server SoC.
We operate like a start-up with the scale of the world's largest cloud provider.
We're looking for a Senior Design Verification Technical Lead- a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Graviton server SoC.
• It starts at product definition- we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written
• It extends into software- we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack
• It reaches into physical design- we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality
• It closes the loop- from spec to silicon, our verification touches every team and every stage of chip development

What Sets Us Apart
- Agentic AI is embedded in our workflow- not as an experiment, but as a core part of how we design and verify chips
- Cutting edge methodologies drive every stage of our verification process
- Relentless innovation- we don't settle; we actively seek new approaches that raise the bar on silicon quality
- We do classic functional verification (SV/UVM/TLM), but beyond that, we touch physical design aspects, to ensure that the quality of our silicon is beyond logical functionality
- Performance optimization at all levels is at the heart of our targets on top of logical correctness verification

A day in the life
As a Senior Design Verification Technical Lead on the Graviton team, you will be responsible for
leading the verification of complex SoC sub-systems, driving cutting-edge verification
methodologies, and ensuring our next-generation Graviton server SoC meets the highest quality
bar before reaching silicon.
What You'll Do
- Develop and execute verification plans for IO sub-systems- covering interconnect
protocols, peripheral interfaces, and system-level integration
- Verify IO sub-system features including interconnect protocols, various accelerators
engines
- C embedded SW programing and SW debug skills
- Build and maintain UVM-based verification environments for IO sub-systems
- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance
- Verify the IO virtualization SMMU/TLB operations, page table walks, translation
granules, and memory attributes (cache-ability, share-ability)
- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions
- Drive coverage closure using functional coverage models, assertion-based verification,
and formal methods where applicable
- Contribute to performance verification — ensuring micro-architectural
implementations meet performance targets alongside correctness

About the team
Diverse Experiences
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