Description
- Bachelor's degree in Electrical Engineering or a related field
- Knowledge of hardware platforms
- Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
- Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing
- Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design
- Experience with industry standard tools and scripting languages (Python or Perl) for automation
- Experience in object-oriented design skills
- 10+ years or more of practical semiconductor ASIC experience including owning end to end DV of major SOC blocks
- Experience with RTL development environments
- Master's degree or Ph.D. degree in Electrical Engineering or related field
- Experience with ARM and various DSP ISAs
- Experience in system-level debugging
- Knowledge of SoC architecture
- Experience communicating technical details verbally and in writing
- Experience with transaction level modeling
- Strong programming skills in SV, UVM and C Knowledge of AMBA bus protocols
- Experience with formal verification methods Experience with Low power verification methods
- Experience with Baremetal processor environments
- Familiarity with industry standard I/O interfaces
- FPGA and emulation platform knowledge
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.
As a Senior Design Verification Engineer, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices. You will participate in the bringup of such blocks on Simulation and Emulation platforms.
You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will:
• Architect and implement verification environments for complex functional blocks
• Create and enhance verification environments using SystemVerilog and UVM
• Develop comprehensive test plans through collaboration with design engineers, SW and architects
• Implement coverage measures for stimulus and corner-case scenarios
• Participate in test plan and coverage reviews
• Drive complex RTL and TB debugs
• Drive UPF based low power verification
• Contribute to verification activities across simulation and emulation platforms
• Work on creating the automation scripts to support DV methodologies
• Create infrastructure to performs system level performance analysis
- Knowledge of hardware platforms
- Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
- Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments, and system testing
- Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design
- Experience with industry standard tools and scripting languages (Python or Perl) for automation
- Experience in object-oriented design skills
- 10+ years or more of practical semiconductor ASIC experience including owning end to end DV of major SOC blocks
- Experience with RTL development environments
- Master's degree or Ph.D. degree in Electrical Engineering or related field
- Experience with ARM and various DSP ISAs
- Experience in system-level debugging
- Knowledge of SoC architecture
- Experience communicating technical details verbally and in writing
- Experience with transaction level modeling
- Strong programming skills in SV, UVM and C Knowledge of AMBA bus protocols
- Experience with formal verification methods Experience with Low power verification methods
- Experience with Baremetal processor environments
- Familiarity with industry standard I/O interfaces
- FPGA and emulation platform knowledge
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.
As a Senior Design Verification Engineer, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices. You will participate in the bringup of such blocks on Simulation and Emulation platforms.
You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will:
• Architect and implement verification environments for complex functional blocks
• Create and enhance verification environments using SystemVerilog and UVM
• Develop comprehensive test plans through collaboration with design engineers, SW and architects
• Implement coverage measures for stimulus and corner-case scenarios
• Participate in test plan and coverage reviews
• Drive complex RTL and TB debugs
• Drive UPF based low power verification
• Contribute to verification activities across simulation and emulation platforms
• Work on creating the automation scripts to support DV methodologies
• Create infrastructure to performs system level performance analysis
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