Senior Design Verification Engineer, Hardware Compute Group

- Bachelor’s degree or higher in EE, CE, or CS.

- 7+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology

- Experience developing UVM test bench, writing testplan, developing tests and verifying the design

- Experience with writing directed/constrained-random tests.

- Experience identifying bugs in architecture, functionality and performance with strong overall debug skills

- Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python or Perl) for automation



- Experience with CPU based verification.

- Experience with high performance industry standard IO interfaces like AMBA AXI4, USB, MIPI etc.

- Domain knowledge in image/video processing

- Strong programming skills in C/C++ and scripting skills in Python and/or Perl

- Excellent verbal and written communication skills


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Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Fire tablets, Fire TV and Amazon Echo. What will you help us create?

As a Sr. Design Verification Engineer at Amazon, you will be part of an advanced engineering and research team that is building world class hardware for devices.

The ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues.


Key job responsibilities
- Define the verification methodology and implement the corresponding test bench infrastructure in advanced HVL to verify world class hardware
- Communicate and work with team members across multiple disciplines
- Deliver detailed test plans for verification of complex digital design blocks by working with design engineers and architects
- Create and enhance constrained-random verification environments using SystemVerilog and UVM and write SVA.
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Close coverage measures to identify verification holes and to show progress towards tape-out
- Participate in test plan and coverage reviews