Silicon Design Flow Methodology and Automation - LEC. 

Location: Penang 15, Penang, Malaysia

Time Type: Full time

Job Description

Job Details:

Job Description:

We are seeking a highly motivated Design Automation Methodology Engineer to define, develop, and maintain scalable automation, flows, and methodologies for silicon design verification and test enablement. This role focuses on Logic Equivalence Check (LEC) and ATPG model generation as critical components of design signoff across RTL, synthesis, ECO, and implementation stages.

The position involves close collaboration with design, ATPG, and CAD teams to deliver robust, automated solutions that improve productivity, correctness, DFT coverage, and simulation quality across multiple technology nodes. If you have strong experience in design automation and methodology development and enjoy owning critical cross-domain flows, we would love to talk to you.

Key Responsibilities:

Tool Development, Flow and Methodology:

• Own and develop end-to-end Logic Equivalence Check (LEC) flows using industry-standard tools such as Cadence Conformal and/or Synopsys Formality.

• Define, document, and maintain LEC methodologies across RTL-to-gate, gate-to-gate, and ECO verification stages.

• Develop and maintain automation and methodology for ATPG model (GLN) generation to support DFT coverage analysis and gate-level simulation.

• Ensure consistency and correctness between LEC, ATPG, and downstream verification and test flows.

• Develop automation, scripts, and infrastructure to improve robustness, scalability, and efficiency of LEC and ATPG-related flows.

• Ensure methodologies align with internal design requirements and industry best practices.

Integration and Support:

• Collaborate closely with DFT and ATPG teams to define requirements and enable efficient GLN model generation and usage.

• Work with RTL, synthesis, and physical design teams to support design execution and signoff.

• Debug complex LEC failures and ATPG model issues, providing clear root-cause analysis and guidance.

• Support ECO implementation and verification flows, including LEC and ATPG model updates for late-stage changes.

• Provide technical support, documentation, and training to design teams on LEC, ATPG, and related methodologies.

• Enable automation to simplify design reuse and migration across projects and technology nodes.

Continuous Improvement:

• Monitor new EDA tool capabilities and emerging technologies to enhance LEC and ATPG flows and methodologies.

• Drive automation initiatives to reduce manual effort, improve turnaround time, and increase design confidence and DFT coverage quality.

• Contribute to cross-domain design automation efforts beyond LEC and ATPG when needed (e.g., STA, physical verification, power, reliability).

• Explore and apply AI/ML techniques where applicable to improve productivity and flow efficiency.

Qualifications:

Education:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Technical Skills:

• 5+ years of experience in silicon design automation, CAD, or methodology development.

• Must have strong scripting and automation skills using Tcl, Python, Perl, shell, or similar languages.

• Strong hands-on experience with Logic Equivalence Check (LEC) using Conformal and/or Formality.

• Proven experience with ECO verification flows, including complex design changes and late-stage fixes.

• Solid understanding of silicon design fundamentals, including RTL, synthesis, implementation, and signoff flows.

• Experience working with advanced technology nodes is a strong plus.

Soft Skills:

• Excellent problem-solving and analytical skills with strong attention to detail.

• Strong communication and collaboration skills, able to work effectively across teams.

• Ability to work independently in a fast-paced, dynamic environment while owning critical methodologies.

Preferred:

• Experience adapting across multiple EDA domains beyond LEC (e.g., STA, physical verification, reliability, power).

• Familiarity with version control systems (e.g., Git, Perforce).

• Experience supporting multiple projects or platforms in a centralized CAD or methodology role.

• Interest in leveraging automation and AI/ML techniques to improve engineering efficiency.

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.