Senior SOC Physical Design/Power Analysis/RDL Engineer

Location: San Jose, California, United States

Time Type: Full time

Job Description

Job Details:

Job Description:

About Altera

Accelerating Innovators — Altera provides leadership programmable solutions that are easy to use and deploy, across the cloud to the edge, enabling limitless possibilities for AI. Our broad portfolio includes FPGAs, SoCs, CPLDs, IP, development tools, system-on-modules, SmartNICs and IPUs, offering the flexibility to accelerate innovation. 

Our innovation in programmable logic began in 1983. Since then we’ve delivered the tools and technologies that empower customers to innovate, differentiate, and succeed in their markets. 

Join us on our journey to becoming the world’s #1 FPGA company!

About the Role:

Altera is seeking a Sr. SoC Physical Design/Power Analysis/RDL Engineer to join our SoC Physical Design Team!

Responsibilities:

• Performs Physical Design Implementation and Power Integrity Static and Dynamic Analysis for SoC block level and Subsystem level. 

• Expertise in BUMP/RDL/MIMCAP planning and implementation

• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.

• Possesses design optimization knowledge to improve product-level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

Minimum Qualifications

Bachelor's degree in computer engineering, electronic Engineering or related field.

5+ years of relevant experience in the following areas:

• Have multiple tape-out experience in deep submicron process nodes

• in depth, extensive knowledge and hands-on experience in physical design flow and relevant EDA tools

• in depth, extensive knowledge and hands-on experience in physical design signoff flow, such as STA flow, LEC flow, ERC flow and DRC flow.

• Hands-on expertise with scripting languages such as Perl, TCL, Python and knowledge of hardware description languages of VHDL and Verilog.

• Experience of mentoring junior team members and charting their development for success.

• Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.

Preferred Requirements:

• Bachelor or master's degree in computer engineering, Electronic Engineering or related field.

• 7+ years of experience in the following areas:

  • Physical design implementation and Static & Dynamic Power analysis expertise in multiple projects with BUMP/RDL/MIMCAP experience.

  • Low power design, tools and methodologies.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.