Senior DFT Design Engineer

Location: San Jose, California, United States

Time Type: Full time

Job Description

Job Details:

Job Description:

About Altera:

Accelerating Innovators — Altera provides leadership programmable solutions that are easy to use and deploy, across the cloud to the edge, enabling limitless possibilities for AI. Our broad portfolio includes FPGAs, SoCs, CPLDs, IP, development tools, system-on-modules, SmartNICs and IPUs, offering the flexibility to accelerate innovation. 
 

Our innovation in programmable logic began in 1983. Since then we’ve delivered the tools and technologies that empower customers to innovate, differentiate, and succeed in their markets. 
 

Join us on our journey to becoming the world’s #1 FPGA company!

About the Role:

The Altera DFT team is looking for a motivated Senior DFT (Design for Testability) Design Engineer to join an industry-leading IC design organization. This is an opportunity to work on cutting-edge technologies including FPGA, processor, DSP, SERDES, IO, 2.5D/3D multi-die packaging, and other advanced solutions that will drive future innovation.

As a Senior DFT Design Engineer, you will be responsible for DFT architecture and implementation, including DFT specifications, test logic insertion, test mode timing constraints, ATPG, and pre-silicon validation. You will also contribute to the development of DFT methodologies and flows to improve pre-silicon and post-silicon validation processes.

This role provides the opportunity to work closely with IP and integration design teams to understand design and functional behaviors of complex circuits, as well as with test development teams to meet manufacturing test requirements for coverage, cost, yield, and silicon bring-up/debug.

Responsibilities:

• Define and implement DFT architectures and specifications for FPGA, processors, DSP, SERDES, IO, and multi-die designs.

• Perform test logic insertion, ATPG pattern generation, and pre-silicon validation for manufacturability and quality.

• Collaborate with IP and integration design teams to align DFT features with design functionality and timing.

• Partner with test development teams to support silicon bring-up, debug, and production readiness.

• Contribute to DFT methodology and automation flows to enhance scalability and efficiency.

• Ensure manufacturability goals are met, including test coverage, test cost optimization, yield improvement, and debug support.

Salary Range

#LI-MD1

Qualifications:

Minimum Qualifications:

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 7+ years of industry experience in the following – OR – Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5+ years of industry experience in the following:

• Experience in DFT design and verification at both RTL and gate level.

• Experience in EDA tools such as synthesis and scan insertion tools, ATPG tools, simulation and debug tools, STA tools

• Design automation experience and proficiency in scripting languages such as Perl/TCL

Preferred Qualifications:

• Experience with test compression, BIST (MBIST/LBIST), and advanced fault models.

• Prior experience with 2.5D/3D multi-die designs and high-speed IO/SerDes DFT.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.