Post-Silicon Validation — FPGA

Location: Bengaluru, Karnataka, India

Time Type: Full time

Job Description

Job Details:

Job Description:

Key responsibilities

• Lead design bring-up on FPGA/silicon

• Own validation covering PVT (corners, voltage/temp sweeps, fmax/margin, stress) and non-PVT (functional, feature, system)

• Define, maintain, and scale test suites (content, automation, overnight runs, fail triage, exit criteria)

• Architect and deliver design/test automation in Python, Tcl, and C; develop and extend VSIP for validation workflows

• Use RTL and on-chip debug to root-cause failures across HW, timing, firmware, and board; apply strong lab and silicon debug skills end-to-end

• Set test plans, coverage expectations, and validation exit criteria for assigned work

• Partner with DV, IPSS, and Customer Support on correlation, integration, and customer/field issues

• Represent validation in milestone reviews and technical escalations

Required qualifications

• B.E. / B.Tech / M.S. in ECE, EE, Computer Engineering, or related

• 5–8 year's experience in post-silicon / FPGA / HW validation or protocol bring-up, aligned to Grade 6 / 7

• Proven ownership of design bring-up and HW validation through production-quality outcomes

• Hands-on PVT planning, execution, and fail analysis

• Strong HW knowledge plus automation in Python, Tcl, and C

• Experience in VSIP development for design/test automation and validation enablement

• Strong debug skills across HW, firmware, board, and silicon (JTAG/on-chip debug, scopes/analyzers, fail isolation to root cause)

• Solid RTL debug ability (Verilog/System Verilog or VHDL)

• FPGA tool and lab proficiency (JTAG/debug, scopes/analyzers, protocol tools as applicable)

• Demonstrated collaboration with DV, IP/integration (IPSS or equivalent), and customer-facing teams

• Clear technical writing for plans, bugs, and status

Qualifications:

Preferred

• Validation knowledge in Ethernet, ANLT, PTP, D-PHY, CPRI, JESD, SerialLite, DP, HDMI, SATA, SAS as added advantage

• Thermal / shmoo / margin characterization

• Board/schematic literacy; basic SI/PI for high-speed links

• Emulation or pre-silicon to post-silicon correlation experience

Soft skills

• Self-motivated technical owner for domain/product validation outcomes

• Strong individual contributor who delivers with limited oversight

• Effective team collaborator across DV, IPSS, Customer Support, and design

Job Type:

Regular

Shift:

Shift 1 (India)

Primary Location:

Bengaluru, Karnataka, India

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.