Performance Power Validation Manager

Location: San Jose, California, United States

Time Type: Full time

Job Description

Job Details:

Job Description:

About Altera:

Accelerating Innovators — Altera provides leadership programmable solutions that are easy to use and deploy, across the cloud to the edge, enabling limitless possibilities for AI. Our broad portfolio includes FPGAs, SoCs, CPLDs, IP, development tools, system-on-modules, SmartNICs and IPUs, offering the flexibility to accelerate innovation. 

Our innovation in programmable logic began in 1983. Since then we’ve delivered the tools and technologies that empower customers to innovate, differentiate, and succeed in their markets. 

Join us on our journey to becoming the world’s #1 FPGA company!

About the Role:

As a Performance Power Validation Manager at Altera, you will lead a team of validation and debug engineers and technicians responsible for ensuring our silicon products meet stringent power, performance, and quality targets. You’ll oversee validation planning, methodology development, execution, and debug for complex silicon systems, driving cross-functional alignment between design, architecture, and manufacturing teams.

This role requires deep technical expertise in silicon performance and power characterization, strong leadership skills, and the ability to deliver results across multiple project phases—from pre-silicon closure through post-silicon validation and high-volume manufacturing.

Key Responsibilities:

• Direct and develop a high-performing team of validation and debug engineers and technicians.

• Define, plan, and execute validation methodologies and test strategies for silicon performance and power metrics.

• Oversee the execution of validation plans for system-level silicon, ensuring alignment with architectural, electrical, power, performance, and area (PPA) goals.

• Collaborate closely with architecture, design, and product engineering teams to drive design optimization, root-cause analysis, and failure resolution.

• Lead post-silicon validation efforts, including bring-up, performance/power measurement, and correlation with pre-silicon models.

• Manage and guide development of automated software tools, scripts, and infrastructure to accelerate validation and data analysis.

• Drive continuous improvement initiatives to enhance validation efficiency, quality, and coverage.

• Deliver status and operations reviews to senior management, highlighting validation progress, risks, and mitigation strategies.

• Provide mentorship, career development, and technical guidance for team members, fostering a culture of innovation, accountability, and excellence.

• Partner with manufacturing and product engineering teams to support yield, binning, and performance characterization activities for volume ramp.

Salary Range 

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$142,600 - $206,500 USD 

*We use artificial intelligence to screen, assess, or select applicants for the position.*

#LI-MD1

Qualifications:

Minimum Requirements:

• Bachelor’s degree or Master's in  in Electrical Engineering, Computer Engineering, or related field.

• 10+ years of relevant experience in validating system performance and power

• 3+ years of direct people management or technical leadership experience.

• Strong understanding of SoC design, bring-up, and validation flows.

• Proven experience with performance and power measurement methodologies, analysis, and optimization.

• Hands-on experience with lab validation tools (oscilloscopes, power analyzers, logic analyzers) and data acquisition systems.

• Proficiency in scripting/programming languages such as Python, Perl, or C/C++.

• Demonstrated success in cross-functional collaboration with design, architecture, and manufacturing teams.

• Strong analytical and problem-solving skills with the ability to lead debug and root-cause activities across multiple domains.

Preferred Qualifications:

• Master’s degree or higher in Electrical Engineering or related field.

• Experience with FPGA-based validation and post-silicon test environments.

• Familiarity with power modeling, performance simulation tools, and correlation techniques.

• Excellent communication, leadership, and team development skills.

• Track record of delivering silicon to mass production with high quality and predictable performance/power outcomes.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.