Real job — pulled straight from Altera’s careers page · Verified June 10, 2026 · No reposts.
Job description
Altera is hiring a Senior Front End ASIC RTL/Logic Design Engineer — a full-time, based in Penang, Malaysia role. Apply directly on Altera's careers page below.
Front End ASIC RTL/Logic Senior Design Engineer
Location: Penang 15, Penang, Malaysia
Time Type: Full time
Job Description
Job Details:
Job Description:
Responsible to lead, define & implement the design (micro-architecture, RTL, linting, CDC, SDC, UPF/power gating, synthesis) of high speed digital design in next generation IO in cutting edge technology node with multi GigaHz design.
Work closely with verification team for design test plan and validation review and back-end team for floor planning, physical implementation, STA timing closure.
Work on post Silicon debug/characterization support of the designs.
Qualifications:
BS/MS or PhD in Electronics Engineering with minimum of 10 years of ASIC frontend experience
Strong in communication, leadership, investigation, problem solving & analytical skill
Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments
Knowledge of Spyglass, Synthesis, STA (PT), UPF, UVM, Spice and DFT.
Knowledge scripting desirable
Job Type:
RegularShift:
Shift 1 (Malaysia)Primary Location:
Penang 15, Penang, MalaysiaAdditional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Get Asic Rtl/logic Design Engineer jobs like this→
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Frequently asked questions
What skills are required for Senior Front End ASIC RTL/Logic Design Engineer at Altera?
The required skills for Senior Front End ASIC RTL/Logic Design Engineer at Altera include: VHDL, Verilog, Shell.
What is the seniority level for Senior Front End ASIC RTL/Logic Design Engineer at Altera?
Senior Front End ASIC RTL/Logic Design Engineer at Altera is a Senior level position.
How do I apply for Senior Front End ASIC RTL/Logic Design Engineer at Altera?
You can view the full description and apply for Senior Front End ASIC RTL/Logic Design Engineer at Altera on EchoJobs: https://echojobs.io/job/altera-front-end-asic-rtl-logic-senior-design-engineer-ouhly.