Real job — pulled straight from Altera’s careers page · Verified September 23, 2026 · No reposts.
Job description
Altera is hiring a FPGA IP Design and Verification Engineer — a full-time, based in Madhapur role. Apply directly on Altera's careers page below.
FPGA IP Design and Verification Engineer
Location: Regus, Madhapur
Time Type: Full time
Job Description
Job Details:
Job Description:
Performs functional logic verification of an FPGA to ensure design will meet specification requirements. Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.
Qualifications:
7+ years of experience in Semiconductor IP Design verification.
Familiarity with HDL languages (VHDL, Verilog, SystemVerilog).
Experience or knowledge in scripting languages such as Tcl, Perl, or Python.
Prior experience or exposure to FPGA tools (Quartus or Vivado) would be advantageous.
Strong willingness to learn new skills and technologies.
Ability to work collaboratively within a team environment.
Good communication skills and ability to clearly present project details and outcomes.
Job Type:
RegularShift:
Shift 1 (India)Primary Location:
Regus, MadhapurAdditional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Get FPGA IP Design and Verification Engineer jobs like this→
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Frequently asked questions
What skills are required for FPGA IP Design and Verification Engineer at Altera?
The required skills for FPGA IP Design and Verification Engineer at Altera include: FPGA, VHDL, Verilog, SystemVerilog, Perl, Python.
What is the seniority level for FPGA IP Design and Verification Engineer at Altera?
FPGA IP Design and Verification Engineer at Altera is a Senior level position.
How do I apply for FPGA IP Design and Verification Engineer at Altera?
You can view the full description and apply for FPGA IP Design and Verification Engineer at Altera on EchoJobs: https://echojobs.io/job/altera-fpga-ip-design-and-verification-engineer-3090t.