Senior Verification Engineer

Department: Hardware

Employment Type: Full Time

Location: West Coast, United States, Hybrid

Key Responsibilities

•  Develop verification plans from design and architecture specifications. 
• Create and maintain SystemVerilog/UVM verification environments. 
• Develop testbenches, assertions, scoreboards and coverage models. 
• Execute directed and constrained-random verification. 
• Analyse coverage and debug RTL and verification issues. 
• Support subsystem and system-level integration activities. 
• Contribute to automation, regression and CI workflows. 
• Participate in design reviews and verification sign-off. 
• Mentor and support junior colleagues

Skills, Knowledge & Expertise

• Degree in Electronic Engineering, Computer Engineering or a related discipline. 
• At least 3 years experience verifying digital ASIC and/or FPGA designs. 
• Strong SystemVerilog and UVM skills. 
• Understanding of RTL design principles and hardware implementation. 
• Experience with coverage-driven and assertion-based verification. 
• Linux proficiency and scripting skills (Python, Tcl or Bash). 
• Strong analytical, debugging and problem-solving skills. 
• Experience using AI to accelerate verification without sacrificing quality 
• Ability to work across multiple teams

• Experience in 4G/5G, NTN, satellite communications or DSP systems. 
• Knowledge of modem architectures and Layer 1 processing. 
• Experience with Formal Verification, FPGA prototyping and CI environments. 
• Familiarity with MATLAB or equivalent modelling tools. 

Job Benefits