Principal Design Team Leader

Department: Hardware

Employment Type: Permanent

Location: Southampton, UK, Hybrid

Key Responsibilities

• Provide strategic vision to inform technical decision-making and planning at a company level , working with colleagues from Algorithm, System Architecture and Software teams.
• Take responsibility for the successful and timely delivery of projects by providing technical leadership
• Provide managerial leadership to build knowledge and support the team development 
• Work closely with the exec team to translate product requirements into hardware team deliverables
• Support discussions with customers during presales and product development
• Oversee the implementation of designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches
• Lead AccelerComm’s engineering methodology, processes, and design techniques, integrating AI where possible.
• Nurture professional growth of team members through regular mentoring, coaching, and feedback

Skills, Knowledge and Expertise

Essential

• Track record of building and leading high performing collaborative teams
• Expert knowledge of RTL design (Verilog, SystemVerilog) for complex ASIC and FPGA products
• A strong skillset in delivery of digital designs for ASIC and FPGA 
• Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis
• Expert user of EDA tools for simulation and synthesis
• Knowledge and appreciation of project management methodologies across the design lifecycle including agile and waterfall, requirements capture and traceability.

Desirable

• Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming) 
• Understanding of UVM verification techniques or practical experience using UVM for IP verification
• Experience with high speed interfaces on and off chip such as AMBA, PCI-E or JESD
• Understanding of using C++/SystemC for design modelling and integration 
• Experience in Technology Readiness Models
• Understanding of system architecture of a multi-disciplinary team project