Senior Logic Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission. 

As Microsoft's cloud business continues to grow, the ability to develop new generation compute silicon is of paramount importance. To achieve this goal, Microsoft’s Cloud Compute Development Organization (CCDO) is seeking seasoned, passionate, driven and intellectually curious Silicon Logic Design Engineer to join our silicon hardware front end logic design team, micro architecting and designing RTL design, design methodology, and design quality for our projects. We are responsible for delivering cutting-edge, CPU-based custom IPs, Subsystems, SOC designs that can perform complex and high-performance functions in the most efficient manner. This team is involved in numerous projects within Microsoft developing CPU based SOCs silicon for data centers. 

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• BS/MS in Electrical Engineering or Computer Science/Engineering 

• 8+ years logic design experience as a part of either CPU, Cache, Fabric, Digital Power Management, DVFS, Sensors, PCMs, Debug, Peripherals and/or SoC development  

• Knowledge of logic design flow including RTL coding, Synthesis, timing constraints, timing closure. 

• Demonstrated expertise in Computer Architecture, Digital Design, IP/SoC design principles as part of SoC and/or IP development. 

Additional Preferred Qualification: 

• Highly Proficient in Verilog/System Verilog coding constructs. 

• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) 

• Demonstrated experience and knowledge of clock crossings, and power/UPF in design 

• Ability to write scripts using Perl, Tcl, Python etc. 

• Familiarity with Industry standard interface protocols is a plus. 

• Familiarity with Formal Equivalence Verification and Power Analysis is a plus. 

• Good verbal and written communication skills. 

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.  
 

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

• Implement the micro-architectural specification in Verilog or System Verilog 

• Continue to grow your micro-architectural knowledge and contribute to unit, sub-system and SOC micro-architecture. 

• Development and Integration of various functional block RTL into SoC RTL 

• Perform design quality checks such as Timing closure, Lint, CDC, Low Power Intent. 

• Interface with verification team to ensure functional correctness. Interface with performance modeling, physical design, design-for-test, and other teams to deliver qualified physical partitions evaluating tradeoffs and delivering high quality design. 

• Exercise the functionality of the block by writing basic tests and debug for various features at IP and SoC levels as deemed necessary. Automate tasks using scripting for efficiency 

• Delight your customers by providing high quality functional blocks on schedule and with professional integrity 

• Challenge the status quo with growth mindset. 

• Mentor junior team members and summer interns for a growing team