Principal Lead Engineer- DFT

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. As a Principal DFT Engineer & DFT Team Lead (Manager) in India site within the Silicon Computing Development team, you & your team will lead product structural test solutions in design: From defining the architecture, establishing methodology, executing test logic insertion, ensuring verification coverage, developing patterns, and finally working with Tester engineers to bring up test vectors on silicon. You will also integrate to the broader team involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems.  We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions most efficiently. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions.

Required Qualifications:

• BS, MS, or Ph.D. in Electrical Engineering/Computer Engineering with over 10 years of experience in the field of Test.
• Excellent understanding of technical and business impacts of DFT features, tools, flows and methods design choices - across all of power, area, performance, effort, test, and debug impact.
  
  

Preferred Qualifications:

• Experience developing Test architecture & micro-arch specifications as it relates to large SOCs along with test insertion techniques for IP's like PLL’s, IO’s & Power circuits.
• Expert at Scan ATPG, Stuck-At, At-Speed insertion, boundary coverage, compression & retargeting flows - using EDA tools like Mentor Tessent or Synopsys TestMax.
• Knowledge of Verilog or System Verilog with experience using simulators and waveform debugging tools.
• Ability to pioneer flows for Gate-level simulation (GLS), perform coverage analysis, and debug for achieving high fault coverage.
• Experience with Static Timing Analysis & constraint generation.
• Experience with ATE and Silicon bring-up with proficiency in 
• Proficient in scripting languages (Tcl & Perl)
• Mentor Tessent / Synopsys tools for Yield & Diagnosis.
• Proactive & self-motivated, eager to learn and contribute in a team environment, committed and accountable.
• Confident problem solver who thrives under pressure to find new, creative solutions.

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

In this high impact role on the team, your responsibilities will include:

• Manage & lead a team of engineers for product DFT deliverables and support individual contributors in their own career growth.
• Work as part of DFX team & closely collaborate with cross-functional teams and customers in a high-paced atmosphere.
• Ability to refine design test methodology and use of industry/home-grown tools to ensure design quality, effectiveness & speed up execution.
• Own block/SoC level DFT arch specification documentation & provide Design-For-Test solutions for increased coverage, optimal design & lower test time.
• Develop state of the art Memory-BIST, Scan patterns & Simulations flows and implementation.
• Provide test plans and engage closely with verification engineers to perform waveform reviews.
• Hold a primary role in enabling silicon by working directly with test engineers to bring up test vectors, and analyzing yield & diagnosis.