Principal Design Verification Engineer

The Artificial Intelligence Silicon Engineering team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible.   We are responsible for delivering cutting-edge AI designs that can perform complex and high-performance functions in an extremely efficient manner. 

We are looking for a Principal Design Verification Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. You will be part of the design verification team, driving many facets of high performance, high bandwidth designs.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.  

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day. 

Required/Minimum Qualifications

• 9+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
• 4+ years of industry experience in design verification involving Ethernet protocol with a proven track record of delivering complex IPs to Application-Specific Integrated Circuit or System on Chips.

Other Qualifications:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Additional or Preferred Qualifications

• 15+ years of industry experience in design verification with a proven track record of delivering complex SoC IPs.
• OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience
• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
• OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.
• DV and optional design Experience with integration of Ethernet IPs into SoCs.  Experience working with 3^rd party IP vendors.
• Experience with IP/SOC verification for a full product cycle from definition to silicon, including writing IP/block or subsystem level architecting DV environment, estimating efforts, test plans, developing tests, debugging failures and coverage signoff.
• Experience of working on AI/Machine Learning (ML)SoCs.
• Experience in post-silicon bring-up of complex SoCs involving Ethernet interface.
• In depth knowledge of verification and debug principles, test benches, System Verilog, Universal Verification Methodology (UVM) and C based test environments.
• Experience in IP level, subsystem level and SoC level verification environments; and verification IP vertical reuse across multiple levels.
• Working knowledge of writing assertions, coverage and / or formal verification.
• Knowledge of industry standard bus interfaces such as Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) and Ethernet protocols.
• Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments.
• Scripting languages such as Zsh, Bash, Python or Perl.

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $133,600 - $256,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $173,200 - $282,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until May 14, 2024.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.  We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

• Own and deliver on design verification of complex Intellectual Property (IP) or Subsystem or System on Chips(SoC) level features.
• Collaborate with the architecture and design teams to ensure the implementation meets both architectural and micro-architectural intent for complex IPs and feature areas of subsystem and SoC.
• Develop test methodologies, strategies, reviews and supervise execution of test plans.
• Develop verification environments involving constrained random stimulus and coverage driven verification; run and debug simulations to drive quality.
• Execute test plans for complex feature areas or products by leveraging teams, as well as through individual contributions.  Set targets for test coverage and strategy to achieve coverage.  Ensure quality of test plan execution across broad areas.
• Apply Agile development methodologies including code reviews, sprint planning, and feature deployment.
• Innovate to improve verification efficiency through methodologies, processes or tools.
• Provide technical leadership through coaching, mentorship, modeling and teamwork.
• Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.