Staff Design Verification Engineer (Boston and Mountain View)

Lightmatter is a photonic computer company redefining what computers and human beings are capable of by building the engines that will power discoveries and drive progress in a sustainable way. With modern human progress relying heavily on computers, the world has hit a dead end with traditional transistors, and the prospect of constantly building data centers is an environmental nightmare. Lightmatter has created a solution in photonic computing: using photons instead of electrons to take advantage of their higher bandwidth. We build chips for artificial intelligence computing. Our architecture leverages the unique properties of light to enable fast and efficient inference and training engines.

As a Design Verification Engineer at Lightmatter, you will find yourself at the heart of a dynamic, interdisciplinary team. Your role will involve close collaboration with our digital design experts, using UVM testbench techniques to rigorously verify their designs. Your responsibilities will include working alongside photonic and analog designers, gaining a deep understanding of their innovative designs, and applying Real Number Modeling (RNM) and AMS verification methods. This critical function ensures the integrity of their work.

Your interaction with the Architecture team will be crucial in comprehending system requirements and spearheading performance verification. This role offers a unique platform to enhance your skills across a spectrum of areas including UVM, AMS modeling, mixed-signal verification, formal verification, emulation, and both performance modeling and verification.

Responsibilities

• Engage collaboratively with teams specializing in digital, photonics, and analog design to develop comprehensive test plans.
• Design and implement UVM testbenches for both subsystem-level and full-chip verification. This includes debugging testbenches, resolving issues, achieving high coverage, and overseeing the final sign-off on Design Verification (DV).
• Develop Real Number Models (RNM) for photonics and analog circuits, conduct AMS verification in conjunction with UVM, and ensure precise model representation. Contribute significantly to the development of the Golden Reference Model (GRM) for design verification. Play an integral role in the execution of emulation and formal verification for DV purposes.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
• 10 years of design verification and Systemverilog experience
• 2+ years of experience in python
• Expertise in developing with the UVM library.
• Experience with simulators such as Xcelium, ModelSim, Questa, or VCS.

Preferred Qualifications

• Master’s degree or higher in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
• Experience with AMS verification
• Experience in formal verification
• Strong problem solver, communicator, and team player