Job Details:

Job Description: 

In Q4 2023, Intel announced Altera will be reported as a separate business unit beginning on January 1, 2024 with ongoing support from Intel. This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future.

Altera, an Intel Company is the industry-leading custom logic solutions to customers since inventing the world's first FPGA reprogrammable logic device in 1984. Join us in developing new technology to provide Intel with a competitive advantage in programmable solutions. If you find it exciting to work in a diverse team that innovates with other Intel advanced technology groups, with other industry leaders, and in academia, then we have your opportunity.

In this position, we are looking for a phenomenal engineer to join our world class engineering team to expand the technology that provides us with advantages in programmable solutions.

• Responsible for the next generation FPGA and SOC ASIC Implementation flow methodology development.

• Defining, implementing and improving the state of the art AI/ML EDA design solutions by sourcing externally or developing the solutions internally.

• Design Automation Engineers are advocates of applying design methodologies to help execute projects effectively and successfully with high quality.

• Providing consultation and EDA tools support to the multiple projects in the area of Place and Route, Design Synthesis.

• Develop in-house algorithms, scripts, programs to support design activities, EDA tools technology infrastructure setup, CAD wrappers, GUIs, EDA tools customization and automation program

Qualifications:

• BSEE/MSEE or equivalent in with minimum of 10 years of experience in IC Design or Design Automation.

• Thorough knowledge in physical design flow from RTL to GDS2 and the challenges posed by advanced technologies. This includes detailed understanding of design synthesis, design partitioning, floor planning, place and route, clock tree synthesis and timing analysis.

• Low Power implementation knowledge is a plus

• 5 to 10 years of Physical Design experience with process nodes 20nm, 10nm or below in ASIC/SoC design flows.

• Full familiarity with Synopsys, Cadence or Mentor Graphics physical design tools

• Programming knowledge in Perl, Python, Tcl/Tk, C++, C-shell and other software languages.

• Strong interpersonal skills and good verbal/written communication skills are required.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Business group:

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.