Job Details:

Job Description: 

Candidate should possess a BSEE or equivalent with 12+ years/MSEE or equivalent with 10+ years design experience in the structural/physical design domain.Additional qualifications include:- Technical lead Role in delivery of multiple SoCs, ASICs, or Sub Chips- Proficient in all aspects of physical design from RTL - GDSII (Synthesis, Floorplan, Auto Place and Route, Clock Tree Synthesis).- Expert level knowledge on Synopsys based implementation tools - ICC2, Fusion Compiler- Experienced in CTS methodologies - CTS, MPCTS, CTMESH- Expertise in High frequency timing closure at sub chip or at SoC- Experienced in Full chip Layout Verification - DRC and LVS- Experience on 7nm and lower a plus- Possesses - Strong Technical Aptitude, Self-Driven, Analytical, Ability to work in diverse teams and Ability to multi-task.- Motivated and Passionate to learn improvements in tool flows and methodologies- Good Communication Skills - Partner with multiple stake holders to deliver the key responsibilities- Hands-on experience with scripting languages such as Python, Perl, TCL

Qualifications:

Candidate should possess a BSEE or equivalent with 6+ years/MSEE or equivalent with 8+ years design experience in the structural/physical design domain.Additional qualifications include:- Technical lead Role in delivery of multiple SoCs, ASICs, or Sub Chips- Proficient in all aspects of physical design from RTL - GDSII (Synthesis, Floorplan, Auto Place and Route, Clock Tree Synthesis).- Expert level knowledge on Synopsys based implementation tools - ICC2, Fusion Compiler- Experienced in CTS methodologies - CTS, MPCTS, CTMESH- Expertise in High frequency timing closure at sub chip or at SoC- Experienced in Full chip Layout Verification - DRC and LVS- Experience on 7nm and lower a plus- Possesses - Strong Technical Aptitude, Self-Driven, Analytical, Ability to work in diverse teams and Ability to multi-task.- Motivated and Passionate to learn improvements in tool flows and methodologies- Good Communication Skills - Partner with multiple stake holders to deliver the key responsibilities- Hands-on experience with scripting languages such as Python, Perl, TCL

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Malaysia, Penang

Business group:

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.