Job Details:

Job Description: 

Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany. As part of Intel's Integrated Device Manufacturer 2.0 (IDM2.0) strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in High-Volume Manufacturing (HVM) at a 2-year cadence going forward. Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.

This job requisition is to seek Senior Defect Metrology Development Engineers for our FSM HVM Global Yield organization, reporting to the Defect Metro Engineering Development manager. Selected candidates will work with other members in defect metro team, other teams in Global Yield org, fab module, yield, integration, and TD team members to achieve yield ramp-up and defect reduction in early production stage, supporting internal and external customers.

Senior Defect Metrology Development Engineer's responsibilities include (but not limited to):

• Collaborate with Technology Development team and Process Integration team to import and setup new technology to production fabs across the globe.
• Identify critical yield limiting defect steps and work with Defect Control team to set production line inspection strategy to protect yield and quality at maximum productivity and lowest cost.

Candidate should possess the following behavioral skills:

• Problem-solving and project/program management experience with strong self-initiative and self-learning capabilities.
• Demonstrated interpersonal skills to perform at leadership role including influencing, engaging, and motivating.
• Proven track record of working across organization through matrix structures to accomplish strategic objectives with conflicting priorities.
• Must demonstrate strong communication skills.
• Good interpersonal skills including influencing, engaging, and motivating.

Qualifications:

Minimum Qualifications:

• Bachelor's degree in in Electrical Engineering, Physics, Chemistry, Materials Science or in a STEM relate Major.
• 4+ years of experience in advanced node semiconductor industry in Defect Engineering / Metrology including task forces and project/program management.
• Experience in defect mechanism and yield impact in semiconductor high-volume production and proven quantified track record of driving down Defect Density.
• Experience in working with Process Integration, Design and OPC teams to identify layout-sensitive defect weak points and address systematic defect issues as well as technology development.

Preferred Qualifications:

• Advanced degree (Master's or Ph.D.) in Electrical Engineering, Physics, Chemistry, Materials Science or in a STEM relate major
• Experience working work with multi-functional, multi-cultural teams.
• Ability to leverage big data analysis to identify process design weaknesses and/or manufacturing weaknesses to propose corrective, data-based solutions.
• Experience in serving external Foundry customers through technical interactions.
• Experience in GAA (Gate-All-Around) technology architecture.
• Experience with module tool impacts to defects, inline parametric and yield through PM life while understanding upstream and downstream impacts to other tools, develop projects at the module level for reduced defectivity.
• Experience in FinFET technology development or high-volume manufacturing with hands-on knowledge of FinFET technology process flow to analyse systematic defect sources and set mitigation actions.
• Experience in module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.

#foundry

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Arizona, Phoenix

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.