Senior Physical Design Synthesis Engineer

The Vision business unit is responsible for creating power-efficient System-on-a-Chip (SoC) ASIC devices for the automotive market.

Responsibilities

• Implement and maintain synthesis flow for ASICs designed by the Vision BU.
• Focus on developing and streamlining new or existing synthesis flows to optimize runtimes, and Power, Performance, Area (PPA) parameters.
• Proactively provide feedback about design, timing, floor planning, timing closure, and other parameters through the stages of RTL to Netlist hand-off.Work in implementing DFT features into synthesis flow as needed.
• Contribute actively in the propagation of block level Design Constraints to the top-level SoC.
• Maintain equivalence checking between different stages of netlist generation and be familiar with relevant ECO implementation flow.
• Maintain a strong and repeatable release mechanism with PD Vendors and make sure there is adherence to predefined release targets and milestones.

Requirements

• Bachelor’s degree in Electrical/Computer Engineering (Master’s preferred)
• 10+ years of complete lifecycle experience with multiple ASICs and technology nodes.
• Demonstrated experience in industry standard Synthesis tools and methodology. 
• Knowledge of Synopsys DC tool suite preferred.
• Strong knowledge of Static Timing Analysis and timing closure techniques.
• Ability to work with PD vendor who may run different Back-End tools (Innovus, ICC etc) compared to synthesis tools used by Vision BU.
• Knowledge of automation tools and scripting languages like TCL, Perl, Python etc.
• Make sure the synthesis scripts can be used by block level designers to help discover and fix any design related issues much earlier in the cycle.
• Be a team player, exhibit a proactive attitude, and problem solving skills.
• Good written and verbal communication skills