Principal Design For Test (DFT) Engineer

The Vision business unit is responsible for creating power-efficient System-on-a-Chip (SoC) ASIC devices for the automotive market.

Responsibilities

• Architect, implement, and deploy DFT flow for ASICs designed by the Vision BU.
• Drive the entire DFT cycle of the ASIC including but not limited to test insertion, test coverage assessment, and at-speed testing, accompanied by implementation knowledge of test pattern development, scan compression, JTAG, IJTAG, Memory BIST and Logic BIST.
• Lead effort in fault simulation including debug and verification.
• Taking new silicon into volume production.
• Ability to step in and help with debugging of existing post-production ASICs.
• Architect re-usable DFT strategies that can be used across generations of similar ASICs and possible different packaging options.
• Interact with members of different teams like Design, Software, and Product to ensure successful deployment and support of DFT features in the ASIC.

Requirements

• 10+ years (Bachelor's + 10 years, Master + 5 years) of complete lifecycle experience with multiple ASICs
• Demonstrated experience in industry standard DFT tools and methodology. Knowledge of Mentor test-tool suite a plus.
• Be involved in synthesis of DFT features and structures. Assist in logical equivalence check between pre and post DFT netlists.
• Create and/or modify to propagate DFT constraints for in-house and external IP and be knowledgeable with regards to DFT related Static Timing Analysis.
• Knowledge of automation tools and scripting languages like TCL, Perl, Python etc.
• Ability to debug DFT related issues in simulation and up to post-silicon bring-up and post-production phases.
• Be a team player and exhibit proactive approach to design, debug, and problem solving
• Good written and verbal communication skills