Staff Design Verification Engineer

Staff Design Verification Engineer

About this role: 

Groq is a machine learning systems company building easy-to-use solutions for accelerating artificial intelligence workloads. Our work spans hardware, software, and machine learning technology. We are seeking an exceptional Design Verification Engineer who is interested to join our Hardware team. You will work closely with internal interdisciplinary teams to drive key aspects of ASIC verification. This is a dynamic fast-paced environment requiring hands-on involvement. You must be responsive, flexible and able to succeed within an open collaborative peer environment.

Responsibilities & opportunities in this role:

• Verify hardware features of accelerator. Work within the Hardware Team to design and verify features on accelerator chips in simulation, emulation and silicon.
• Build testbenches from scratch. Leverage your understanding on building randomly constrained verification simulation testbenches.
• Grow verification infrastructure. Be instrumental in setting up eda flows and processes to aid to improve verification productivity and regression management.
• Be a productivity multiplier. Contribute to identifying and adopting engineering best practices within the Design Verification team and interactions with cross-functional teams at Groq.
• Innovate. Contribute to developing future verification strategies for validating future accelerator chips and hardware architectures for ML workloads. Be a self-starter.

Ideal candidates have/are:

• Ability to build strong cross-functional team relationships
• Good written and oral communication skills; strong technical documentation skills
• Highly self-motivated and directed; self-confidence and self-starter
• Keen attention to detail
• Proven analytical and problem-solving abilities
• Ability to effectively prioritize and execute tasks in a high-pressure environment
• Experience working in a team-oriented, collaborative environment

Qualifications for this role:

• BS degree in electrical engineering, or related fields, or equivalent practical experience; advance degrees (MS or PhD) is a plus
• 10+ years design verification experience of building testbenches environments and design verification processes
• Excellent verbal and written communication skills to clearly communicate concepts in written and verbal form to stakeholders.
• Experience with building block and SOC testbench development
• Good familiarity with SystemVerilog and UVM
• Good familiarity with randomly constrained testing methodologies.
• Good familiarity with power verification strategies and UPF
• Experience in Python and/or Perl scripting
• Knowledge of ASIC design flow
• Proven track record of delivering bug-free silicon
• Knowledge of silicon bring-up and ATE test support desired
• Experience on validation on emulation platforms desired