Astera Labs

Tech Lead DV Engineer

Santa Clara, CA
USD 206k - 216k
Machine Learning
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Description

Astera Labs Inc., a semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.

Date Posted: 2/6/2023

Position:               Tech Lead DV Engineer (multiple openings)

Job Location:     Astera Labs, Inc., 2901 Tasman Drive, Suite 204, Santa Clara, CA 95054 USA

With a high degree of independent decision making and minimum supervision, the Tech Lead DV Engineer will be responsible for the following duties:

  • Defining a design verification, emulation or prototype methodology for a SoC which can ensure that the product will comply to a variety of industry standards (PCIe, I2C, Ethernet, etc.) and meet numerous customer specific requirements;
  • Developing an SoC verification environment based on Universal Verification Methodology (UVM) principles to enable functional verification and formal verification of SoC designs;
  • Implementing test plans, test cases, and test procedures (Verilog, C or Unix based) to ensure complete functional and non-functional test coverage for high-speed communication protocols and associated verification IPs (VIPs);
  • Running tests and regression simulations, reviewing results, and identifying root cause for any/all failing cases using function simulation or prototyping;
  • Implementing necessary changes in the register transfer language (RTL) design based on simulation results and root cause analysis.

This position requires a U.S. Master’s degree or foreign equivalent, in EE, Com Eng, CE, or closely related field, and two (2) years of experience as a Design Engr, Ver. Engr, SW Engr/Dvlpr, Memb. of Tech Staff, or closely related occupation.

Must have experience with:

  • UVM (Universal Verification Methodology);
  • High speed DDR interface (DDR4) or PCI-Express;
  • Verilog;
  • System Verilog;
  • Object oriented programming (C/C++).

Salary: $206,000 - $216,000 per year; Full-Time.

Contact: Priya Srivastava, HR Manager, priya.srivastava@asteralabs.com

 

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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