Astera Labs Inc., a semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
Date Posted: [3/21/2023]
Position: Senior Principal Hardware Engineer (multiple openings)
Job Location: Astera Labs, Inc., 2901 Tasman Drive, Suite 204, Santa Clara, CA 95054 USA
With a high degree of independent decision making and minimum supervision, the Senior Principal Hardware
Engineer will be responsible for the following duties:
- Design and support Astera Labs' portfolio of connectivity products upon state of the art electronic packages
- Work with product team to define the board architecture, system-level integrity specifications, and test
methodologies and plans
- Perform high speed interface signal and power integrity analysis and simulation for critical interfaces such as
Ethernet, PCIE 5.0/6.0, DDR4/5, USB, and SATA,
- Conduct product debugging and lab measurements
- Develop advanced technologies and features for future production
This position requires a U.S. Master’s degree or foreign equivalent, in Electrical Engineering, Electronic Engineering, Communications Engineering, or closely related field, and three (3) years of experience as a Hardware Engr, Application Engr, Electrical Egr, Analog Engr, Memb. of Tech Staff, or closely related occupation.
Must have experience with:
- Frequency-domain simulation
- Time-domain analysis and simulation
- Electromagnetic field theory
- High-speed interface validation
- Simulation and lab measurement techniques
- PCIe-gen 6/5 Or 25/50/100 Gbps Or DDR 5/4
Salary: $232,000 - $242,000 per year; Full-Time.
Contact: Priya Srivastava, HR Manager, priya.srivastava@asteralabs.com
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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