Sr. Design Verification Methodology Engineer – (UVM/SV)

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_   THE ROLE: The AMD Verification Methodology and Technology (VMT) team delivers verification methodology and technology for all AMD teams and products. Team member will be working with global teams on the verification methodologies and technologies covering design technology, functional verification technology, coverage, debug, low power technology, and automation methodologies. THE PERSON: A successful candidate in this senior position is expected to excel in analytical thinking, problem solving, organizing data, gathering requirements, planning and execution. He/she needs to be a self-starter who collaborates well with team members and customers alike to successfully drive tasks to completion. KEY RESPONSIBILITIES: The successful candidate will assume technical responsibilities and hands-on technical architect role responsible for providing complex design methodologies in the hardware design verification space. The following is a list of key responsibilities that the candidate will assume: Be a part of a team of technical experts in design verification & testbenches in AMD's Central R&D team Be hands on technical contributor in the space of hardware description languages such as Verilog, testbench languages such as SystemVerilog and an expert in digital design Play an expert role in verification methodologies and have extensive knowledge and multi-year hands on experience testbench-based random design Possess and utilize in-depth knowledge in functional and code coverage technology gathering, management and utilization including concepts around coverpoints, covergroups, etc. Drive methodology around SOC/IP verification, Verification IPs, UVCs and bus functional models Demonstrate and utilize strong debugging skills in SOC/IP design & verification tools Provide methodologies to achieve fast coverage closure mechanisms Provide methodologies on logic functional verification technology and methodology (UVM) Have knowledge of Verification Management tools and methodologies Play a strong role in understanding AMD's existing systems, creating new ones, defining roadmaps, creating methodologies around DV and VIPs, UVCs, BFMs Provide leadership in testbench technologies such as randomization, coverage, stimuli reuse Collaborate with EDA vendors for tool trainings, evaluation and deployment and drive EDA vendors toward common solutions across AMD Utilize experience in Verilog/SystemVerilog, register descriptions and functional modeling Provide guidance in complex system design abstraction and automation around it including IP-XACT technology and methodology R&D Utilize strong knowledge on hardware register design, verification and implement automation around automatic register flow generation PREFERRED EXPERIENCE: Hands-on deep technical industry experience with Verilog, testbench, UVM a must Strong understanding of digital electronic design and design verification processes Versatility in verification methodology like UVM as well as knowledge of industry standard tools for DV, testbenches, VIPs, etc. expected Be aware of the latest developments in the industry on Design Verification topics Knowledge of Verilog, C, C++, Perl, Python, Ruby, and other scripting languages IP-XACT knowledge a plus Emulation and/or simulation acceleration experience is a plus Experience in EDA industry tools, scripting and software development practices Hardware/software co-verification and validation methodologies is a plus Work on low power technology (UPF, VSI/VCLP, NLP, PTPX, Power analysis) is a plus Must possess strong interpersonal and communication skills and needs to be a team player ACADEMIC CREDENTIALS: Bachelors, Master, or PhD degree in Electrical or Computer engineering LOCATIONS: Austin, TX #LI-DD3 At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

  THE ROLE: The AMD Verification Methodology and Technology (VMT) team delivers verification methodology and technology for all AMD teams and products. Team member will be working with global teams on the verification methodologies and technologies covering design technology, functional verification technology, coverage, debug, low power technology, and automation methodologies. THE PERSON: A successful candidate in this senior position is expected to excel in analytical thinking, problem solving, organizing data, gathering requirements, planning and execution. He/she needs to be a self-starter who collaborates well with team members and customers alike to successfully drive tasks to completion. KEY RESPONSIBILITIES: The successful candidate will assume technical responsibilities and hands-on technical architect role responsible for providing complex design methodologies in the hardware design verification space. The following is a list of key responsibilities that the candidate will assume: Be a part of a team of technical experts in design verification & testbenches in AMD's Central R&D team Be hands on technical contributor in the space of hardware description languages such as Verilog, testbench languages such as SystemVerilog and an expert in digital design Play an expert role in verification methodologies and have extensive knowledge and multi-year hands on experience testbench-based random design Possess and utilize in-depth knowledge in functional and code coverage technology gathering, management and utilization including concepts around coverpoints, covergroups, etc. Drive methodology around SOC/IP verification, Verification IPs, UVCs and bus functional models Demonstrate and utilize strong debugging skills in SOC/IP design & verification tools Provide methodologies to achieve fast coverage closure mechanisms Provide methodologies on logic functional verification technology and methodology (UVM) Have knowledge of Verification Management tools and methodologies Play a strong role in understanding AMD's existing systems, creating new ones, defining roadmaps, creating methodologies around DV and VIPs, UVCs, BFMs Provide leadership in testbench technologies such as randomization, coverage, stimuli reuse Collaborate with EDA vendors for tool trainings, evaluation and deployment and drive EDA vendors toward common solutions across AMD Utilize experience in Verilog/SystemVerilog, register descriptions and functional modeling Provide guidance in complex system design abstraction and automation around it including IP-XACT technology and methodology R&D Utilize strong knowledge on hardware register design, verification and implement automation around automatic register flow generation PREFERRED EXPERIENCE: Hands-on deep technical industry experience with Verilog, testbench, UVM a must Strong understanding of digital electronic design and design verification processes Versatility in verification methodology like UVM as well as knowledge of industry standard tools for DV, testbenches, VIPs, etc. expected Be aware of the latest developments in the industry on Design Verification topics Knowledge of Verilog, C, C++, Perl, Python, Ruby, and other scripting languages IP-XACT knowledge a plus Emulation and/or simulation acceleration experience is a plus Experience in EDA industry tools, scripting and software development practices Hardware/software co-verification and validation methodologies is a plus Work on low power technology (UPF, VSI/VCLP, NLP, PTPX, Power analysis) is a plus Must possess strong interpersonal and communication skills and needs to be a team player ACADEMIC CREDENTIALS: Bachelors, Master, or PhD degree in Electrical or Computer engineering LOCATIONS: Austin, TX #LI-DD3

At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

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